CSR--EHS: Collaborative Research: Hybrid Timing Analysis via Multi-Mode Execution

当前针对安全关键型嵌入式系统的软件设计要求严格遵守编码标准，以确保安全性和可靠性。实时嵌入式系统的一个关键附加要求是软件组件的可预测计时行为，这要求确定嵌入式软件的最坏情况执行时间(WCET)的界限。虽然静态时序分析为WCET提供了可验证的范围，但由于芯片制造规模的原因，它无法跟上体系结构创新和硬件性能变化的步伐。这项工作为WCET的界定提供了一种全新的方法，有三个主要贡献：(1)不是模拟执行，而是提升硬件的实际执行来评估任务的WCET。这种方法不仅使繁琐的硬件建模变得不必要，而且还确认了正确的行为，而不考虑体系结构的复杂性或硬件的变化。(2)通过现场可编程门阵列综合，对该方法及其复杂度进行了评估。这将评估设计的可行性并验证原型实现。(3)在合作设计空间探索中研究了先进建筑特征的影响，旨在提供可预测性和严格的WCET界限。该项目的研究通过为安全关键型嵌入式实时系统的硬件和软件设计提供高置信度界限，通过支持评估执行时间来增强硬件体系结构，以及通过协同设计定制硬件功能来提高可预测性，从而促进了现有的科学和技术。这些能力直接有利于软件控制的安全性和可靠性，例如飞机和汽车组件，从而有助于嵌入式系统的高置信度设计。

Current software design for safety-critical embedded systems requires stringent compliance with coding standards to ensure safety and reliability. A key additional requirement for real-time embedded systems is predictable timing behavior of software components, which requires that bounds on the worst-case execution time (WCET) of embedded software be determined. While static timing analysis yields verifiable bounds on the WCET, it cannot keep pace with architectural innovations and hardware performance variation due to chip fabrication scaling. This work contributes a fundamentally new approach to bounding the WCET with three major contributions: (1) Instead of simulating execution, actual execution in hardware is promoted to assess the WCET of a task. This approach not only renders tedious hardware modeling unnecessary but also confirms correct behavior regardless of architectural complexity or hardware variation. (2) The approach and its complexity are evaluated by FPGA synthesis. This assesses the feasibility of the design and validates a prototype implementation. (3) The impact of advanced architectural features is studied in a co-design space exploration, aimed to provide predictability and tight WCET bounds. The research conducted in this project advances existing science and technology through novel techniques in hardware and software design for safety-critical embedded real-time systems by providing high-confidence bounds on execution times; enhancing hardware architectures with support to assess execution times; and customizing hardware features via co-design to improve predictability. These capabilities directly benefit safety and reliability of software controlling, for example, aircraft and components of cars, thereby aiding the high-confidence design of embedded systems.