CAREER: Process Variation Aware Embedded MPSoC Synthesis

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The objective of this NSF CAREER research is to develop process variation aware design methodologies for the synthesis of embedded systems in nanometer scale CMOS technology. Many embedded systems are heterogeneous multiprocessor system-on-chip (MPSoC) architectures. The reliance on deep sub-micron process technologies for the fabrication of embedded multiprocessor system-on-chips gives rise to concerns about process variations, which can cause significant performance variations for a design. Although designing for worst-case process margins is the traditional approach to deal with outliers, the degree of variability encountered in the new process technologies makes this option nonviable. The existing deterministic embedded system design methodologies may result in unexpected performance discrepancy or a pessimistic performance estimation, and may end up using excess resources to guarantee real-time constraints, due to overly conservative design approaches. This research proposes a design paradigm shift from today's deterministic design to statistical or probabilistic design. Specifically, this proposal aims at: (1) developing hierarchical statistical analysis methodologies to facilitate embedded MPSoC synthesis; (2) developing process-variation-aware hardware synthesis techniques; (3) developing process variation aware software worst case execution time (WCET) analysis and optimization techniques for embedded applications; (4) developing process variation aware hardware/software co-synthesis techniques. The education part of this program includes: the enhancement of existing curriculum by integrating new course modules on process variations to complement and upgrade the core courses; the broad dissemination of the results via research publications, courses, seminars, tutorials, and workshops; and the development of software components that are disseminated to the research community and beyond.