CSR-SMA: Toward Model-Driven Multilevel Analysis and Optimization of Multicomponent Computer Systems

该项目旨在实现跨计算系统的多个级别的模型驱动优化，包括体系结构、编译器、算法和应用层，以实现性能、功率和生产率等多个目标。主要目标是开发一个模型驱动的多层次、多目标优化的综合框架，重点关注芯片多处理器(CMPS)和大规模、稀疏工程和科学应用。关键活动涉及开发(I)参数模型以组成应用程序、体系结构和编译器转换的模型，(Ii)在对不确定性建模的同时确定多目标、最优或帕累托最优设计的优化框架，以及(Iii)用于计算系统的多水平优化的本科生和研究生课程，所提出的技术在大、中尺度产生可与随机优化技术一起用来确定最优设计选择的指标。中尺度指标是通过模拟一个串联的离散时间马尔可夫链模型(C-DT-MCM)获得的，该模型同时包含了多层优化的确定性和随机性方面及其影响。这样的C-DT-MCM可以非常有效地模拟以获得踪迹，然后可以使用统计技术与详细的硬件模拟的踪迹进行比较。使用这种方法，只需要使用当前的模式来详细研究有希望的设计选项，例如详细的硬件模拟器，这对于更大的CMP体系结构来说可能会慢得令人望而却步。

This project seeks to enable model-driven optimizations spanningmultiple levels of a computing system including the architecture,compiler, algorithm and application layers, for multiple objectivessuch as performance, power and productivity. A primary goal is todevelop a comprehensive framework for model-driven multilevel,multiobjective optimizations with a focus on chip multiprocessors(CMPs) and large-scale, sparse engineering and scientific applications.Key activities concern developing (i) parameterized models tocompose models of the application, architecture and compilertransformations, (ii) an optimization framework to determinemultiobjective, optimal or pareto-optimal designs while modelinguncertainties, and (iii) undergraduate and graduate courses on themethodology for multilevel optimizations of computing systems, The proposed techniques yield metrics at coarse- and medium-scalesthat can be used with stochastic optimization techniques to determineoptimal design choices. The medium-scale metrics are obtained bysimulating a concatenated discrete time Markov Chain model (C-DT-MCM)which incorporates both the deterministic and stochastic aspectsof multilevel optimizations and their impacts. Such C-DT-MCMs canbe simulated very efficiently to obtain traces which can then becompared using statistical techniques with those from detailedhardware simulation. Using this approach, only promising designoptions need be studied in detail, using current modalities, suchas detailed hardware simulators, which can be prohibitively slowfor larger CMP architectures.