CSR-SMA: Toward Model-Driven Multilevel Analysis and Optimization of Multicomponent Computer Systems

该项目旨在使模型驱动的优化跨越计算系统的多个层次，包括架构、编译器、算法和应用层，以实现性能、功率和生产力等多个目标。主要目标是开发一个全面的框架，用于模型驱动的多层次，多目标优化，重点是芯片多处理器（cmp）和大规模，稀疏工程和科学应用。主要活动涉及开发(i)参数化模型，以组成应用程序，体系结构和编译器转换的模型，（ii）在建模不确定性时确定多目标，最优或帕累托最优设计的优化框架，以及（iii）关于计算系统多层次优化方法的本科和研究生课程。所提出的技术产生的指标在粗和中等规模，可以与随机优化技术一起使用，以确定最优的设计选择。通过模拟一个串联离散时间马尔可夫链模型（C-DT-MCM）获得了中等尺度的度量，该模型结合了多层优化及其影响的确定性和随机方面。这样的c - dt - mcm可以非常有效地模拟以获得迹线，然后可以使用统计技术与来自详细硬件模拟的迹线进行比较。使用这种方法，只需要详细研究有前途的设计，使用当前的模式，例如详细的硬件模拟器，这对于更大的CMP架构来说可能会非常慢。

This project seeks to enable model-driven optimizations spanningmultiple levels of a computing system including the architecture,compiler, algorithm and application layers, for multiple objectivessuch as performance, power and productivity. A primary goal is todevelop a comprehensive framework for model-driven multilevel,multiobjective optimizations with a focus on chip multiprocessors(CMPs) and large-scale, sparse engineering and scientific applications.Key activities concern developing (i) parameterized models tocompose models of the application, architecture and compilertransformations, (ii) an optimization framework to determinemultiobjective, optimal or pareto-optimal designs while modelinguncertainties, and (iii) undergraduate and graduate courses on themethodology for multilevel optimizations of computing systems, The proposed techniques yield metrics at coarse- and medium-scalesthat can be used with stochastic optimization techniques to determineoptimal design choices. The medium-scale metrics are obtained bysimulating a concatenated discrete time Markov Chain model (C-DT-MCM)which incorporates both the deterministic and stochastic aspectsof multilevel optimizations and their impacts. Such C-DT-MCMs canbe simulated very efficiently to obtain traces which can then becompared using statistical techniques with those from detailedhardware simulation. Using this approach, only promising designoptions need be studied in detail, using current modalities, suchas detailed hardware simulators, which can be prohibitively slowfor larger CMP architectures.