Electrical Overstress Protection for System-in-a-Package

系统级封装的电气过应力保护

• 批准号: 0725406
• 负责人: Elyse Rosenbaum
• 金额: $ 30万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-15 至 2012-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0725406&HistoricalAwards=false
• 关键词: Electrical; Overstress; Protection; System; Package

Proposal 0725406Intellectual MeritThe objective of this research is to explore the response of system-in-a-package to electrical overstress events, and to develop the know-how to protect against these without compromising the system performance. The approach is to design an electrostatic discharge protection network for the system, and then use circuit simulation to study its response to various electrical stresses. Electrical overstress events are full-system phenomena, yet the circuit to be simulated must be of limited size. The researchers will identify the typical failure spots in system-in-a-package and construct circuits that produce the correct response at these locales. Models of the various elements in the circuit will be constructed based on the results of electrical measurements and 3-dimensional electromagnetic simulation. Measurements are made using short duration, high amplitude pulses that emulate electrostatic discharges. Broader ImpactElectrostatic discharge / electrical overstress is responsible for more than half of integrated circuit failures. The implications of using vertical stacking to integrate multiple die in one package are not known, nor is known the impact of integrating die that were fabricated in disparate technologies. In a system-on-a-chip, the common silicon substrate provides a favorable path for dissipation of static charge; for system-in-a-package, this low impedance path is absent. This research will identify reliability hazards unique to system-in-a-package and provide solutions. The research team will offer an intensive, engineering outreach program to 4th and 5th grade children at a Title I school. The outreach modules tie into the research program. A workshop on microelectronics will be provided for elementary school teachers, and for the undergraduate Engineering Advocates.

建议0725406知识价值本研究的目的是探索系统级封装对电气过应力事件的响应，并开发在不影响系统性能的情况下防止这些事件的专有技术。该方法是为系统设计一个静电放电保护网络，然后利用电路仿真研究其对各种电应力的响应。电过应力事件是全系统现象，但要模拟的电路必须是有限的大小。研究人员将确定系统级封装中的典型故障点，并构建在这些位置产生正确响应的电路。电路中各种元件的模型将根据电气测量和三维电磁仿真的结果构建。测量是使用短持续时间，高振幅的脉冲，模仿静电放电。更广泛的影响静电放电/电气过应力是一半以上集成电路故障的原因。使用垂直堆叠将多个管芯集成在一个封装中的含义尚不清楚，也不清楚集成以不同技术制造的管芯的影响。在片上系统中，公共硅衬底为静电荷的消散提供了有利的路径;对于系统级封装，这种低阻抗路径是不存在的。这项研究将确定系统级封装特有的可靠性危害，并提供解决方案。该研究小组将提供一个密集的，工程外展计划，以第四和第五年级的孩子在标题一所学校。外展模块与研究计划相结合。将为小学教师和本科工程倡导者举办一个微电子讲习班。