SGER: Investigating the Turbo Principle for Reliable Energy-Efficient Networks-on-Chip

ECCS-0733450P。Ampadu，罗切斯特大学智力优势：这项探索性研究调查了涡轮原理在可靠的纳米级片上网络设计中的可行性和适用性。turbo原理涉及三个主要思想-（1）采用空间、信息和时间冗余的协作编码和解码;（2）传播噪声的伪随机交织;（3）用于降低复杂度和能量效率的迭代估计。这项研究将研究硬件兼容的方法，包括合作，交织和迭代估计联合提高可靠性和更好地管理增加布线复杂性所造成的芯片上集成的数千个核心。具体的研究任务包括：（1）开发适用于片上网络的联合可靠性和能效指标;（2）确定优化空间冗余的合适互连拓扑;（3）研究分组交织与片上交换机和路由器的适当组织，以实现节点处的低延迟数据聚合;（4）开发特定的涡轮式编码和解码算法，以实现接近最佳的联合可靠性和能源效率。更广泛的影响：这项研究将使纳米电子和新兴技术社区受益，因为物理互连和可靠性是超大规模集成的关键瓶颈的前沿。在这项研究中获得的基础知识将传播给研究人员和从业人员，加速片上网络和多核片上系统以及其他新兴纳米技术的研究。这项探索性研究的结果将在PI开发的研究生课程中找到直接应用和协同作用，称为VLSI错误控制系统。此外，这项研究将培养一名研究生，重点研究芯片上的网络，信息理论，通信和集成系统设计。PI积极参与社区外展到当地初中和高中，与教师和校长密切合作，以促进在科学和工程的代表性不足的群体的参与。计划与当地高中一起举办一个实验讲习班，探讨通过系统可靠性创新培养企业家精神的方法，鼓励参与，特别是代表性不足的群体的参与。在参加研讨会之前，PI和一些当地高中教师将共同开发一个关于片上网络的基础课程

ECCS-0733450P. Ampadu, University of RochesterIntellectual Merit:This exploratory research investigates the feasibility and applicability of the turbo principle to the design of reliable nanometer scale networks-on-chip. The turbo principle involves three main ideas-(1) cooperative encoding and decoding employing spatial, information, and temporal redundancy; (2) pseudo-random interleaving that spreads noise; (3) iterative estimation for reduced complexity and energy-efficiency. This research will examine hardware-amenable methods that embrace cooperation, interleaving, and iterative estimation jointly to improve reliability and better manage the increased wiring complexity resulting from on-chip integration of thousands of cores. Specific research tasks to be performed include (1) developing joint reliability and energy-efficiency metrics appropriate for networks-on-chip; (2) determining suitable interconnection topologies that optimize spatial redundancy; (3) investigating packet interleaving with proper organization of on-chip switches and routers to enable low-latency data aggregation at the nodes; (4) developing specific turbo-like encoding and decoding algorithms for near-optimal joint reliability and energy-efficiency.Broader Impact:This research will benefit both the nanoelectronics and emerging technologies communities, as physical interconnect and reliability are at the forefront of critical bottlenecks for ultra-large scale integration. The foundational knowledge acquired in this research will be disseminated to researchers and practitioners, accelerating research in networks-on-chip and multicore systems-on-chip, as well as other emerging nanoscale technologies. Results from this exploratory research will find direct application and synergy in a graduate level course developed by the PI, termed VLSI Error Control Systems. Further, this research will train one graduate student in a focused interdisciplinary study of networks-on-chip, information theory, communications, and integrated systems design. The PI is actively engaged in community outreach to local middle and high schools, working closely with teachers and principals to foster increased participation of underrepresented groups in science and engineering. An experimental workshop that explores methods for building entrepreneurship through innovations in systems reliability is planned with local high schools, encouraging participation, particularly from underrepresented groups. A rudimentary course on networks-on-chip will be jointly developed by the PI and some local high school teachers prior to participation in the workshops