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SaTC: CORE: Small: Finding and Mitigating Side-channel Leakage in Embedded Architectures

SaTC: CORE: Small: Finding and Mitigating Side-channel Leakage in Embedded Architectures
SaTC:核心:小型:查找并减轻嵌入式架构中的侧通道泄漏
批准号:
1931639
负责人:
Paul Ampadu
金额:
$50.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2019
资助国家:
美国
项目状态:
已结题
起止时间:
2019-10-01 至 2023-09-30

项目摘要

项目成果

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中文摘要
翻译
智能家居、汽车、飞机、医疗和工业应用中的电子设备越来越能够使用自己的嵌入式处理器现场处理信息。虽然嵌入式处理器使生活更轻松,但它们也为窃取或破坏我们的敏感数据打开了大门。恶意攻击者可以监控设备内部和周围的功率或辐射特征,并使用侧信道攻击来发现其秘密。该研究项目将提高嵌入式程序员编写具有侧通道保护的代码的能力,并提供工具,以在设计过程的早期验证其代码的侧通道抵抗力。该项目将利用位切片代码的潜力,实现嵌入式平台上高度确定性的软件执行,同时促进自动插入对抗侧通道攻击的对策。这项工作将开发一个过程来重新排序通用代码成位切片的形式,其中一个指令字的每个位是有效地独立处理。接下来,针对电源侧信道攻击的布尔对策将自动插入到代码中。嵌入式对策的有效性将通过一种新的组合,侧通道泄漏检测方法在模拟和目标原型阶段进行验证。最后,泄漏缓解算法将迭代地升级位切片的代码。这项研究可能会导致新的处理器架构和安全的嵌入式应用程序的指令集,在一个时代,先天的安全性是一样重要的性能和效率。这些技术将支持现有的处理器架构,并且与现有的嵌入式设计方法兼容。此外,这些方法将导致侧通道感知设计在电子设计自动化工作流程中的集成,支持新的和改进的架构的开发。该项目的成果将加强密码工程和硬件安全方面的研究生课程。该项目还将利用行业合作来转移成果和设计工具。该项目的成果,包括出版物、代码和示例,将在https://sites.google.com/view/bitslice-mitigation在线托管。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Electronic devices found in a smart home, automobile, airplane, medical, and industrial applications are becoming more capable of on-the-spot processing information with their own embedded processors. While embedded processors make life easier, they also open the door to theft or corruption of our sensitive data. Malign actors can monitor power or radiation signatures in and around a device, and discover its secrets using side-channel attacks. This research project will improve the embedded programmers' capability to write code with side-channel protection and provides tools to verify their code's side-channel resistance early in the design process.The project will exploit the potential of bit-sliced code to achieve highly deterministic software execution on embedded platforms while facilitating automated insertion of countermeasures against side-channel attacks. This work will develop a process to reorder general-purpose code into bit-sliced form, where each bit of an instruction word is effectively processed independently. Next, Boolean countermeasures against power side-channel attacks will be inserted automatically into the code. Effectiveness of embedded countermeasures will be verified through a novel combination of side-channel leakage detection methodologies during simulation and target prototyping stages. Finally, a leakage mitigation algorithm will iteratively upgrade the bit-sliced code.This research may lead to novel processor architectures and instruction sets for secure embedded applications, in an era where innate security is as important as performance and efficiency. The techniques will support existing processor architectures, and they are compatible with existing embedded design methodologies. Additionally, the methods will lead to the integration of side-channel aware design in the electronic design automation workflow, supporting the development of new and improved architectures. The results of this project will enhance graduate-level courses on cryptographic engineering and on hardware security. The project will also leverage industry collaborations to transfer results, and design tools. The results of this project, including publications, code, and examples, will be hosted online at https://sites.google.com/view/bitslice-mitigation. After the completion of the project, the website will remain online as a reference repository.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(11)
专著(0)
科研奖励(0)
会议论文
Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption
付出代价的侧信道阻力:基于 ARX 的认证加密的比较
DOI: 10.1109/fpl50879.2020.00040
发表时间: 2020
期刊: 2020 30th International Conference on Field-Programmable Logic and Applications (FPL
影响因子: --
作者: [Coleman, Flora, Rezvani, Behnaz, Sachin, Sachin, Diehl, William]
通讯作者: Diehl, William
A Scalable DC/DC Converter with Fast Load Transient Response and Security Improvement
具有快速负载瞬态响应和安全性改进的可扩展 DC/DC 转换器
DOI: 10.1109/socc56010.2022.9908087
发表时间: 2022
期刊: 2022 IEEE 35th International System-on-Chip Conference (SOCC
影响因子: --
作者: [Liu, Xingye, Ampadu, Paul]
通讯作者: Ampadu, Paul
A Scalable Integrated DC/DC Converter with Enhanced Load Transient Response and Security for Emerging SoC Applications
具有增强负载瞬态响应和安全性的可扩展集成 DC/DC 转换器,适用于新兴 SoC 应用
DOI: 10.1109/mwscas54063.2022.9859336
发表时间: 2022
期刊: 2022 IEEE International Symposium on Circuits and Systems (ISCAS
影响因子: --
作者: [Liu, Xingye, Ampadu, Paul]
通讯作者: Ampadu, Paul
Distributed On-Chip Power Supply for Security Enhancement in Multicore NoC
用于增强多核 NoC 安全性的分布式片上电源
DOI: 10.1109/socc52499.2021.9739219
发表时间: 2021
期刊: 2021 IEEE 34th International System-on-Chip Conference (SOCC
影响因子: --
作者: [Liu, Xingye, Ampadu, Paul]
通讯作者: Ampadu, Paul
11
    CAREER: Towards Reliable Hybrid CMOS/Nanoelectronics On-Chip Interconnection Networks
    • 批准号:
      0954999
    • 项目类别:
      Standard Grant
    • 资助金额:
      $40.0万
    • 财政年份:
      2010
    • 负责人:
      Paul Ampadu
    • 依托单位:
    Dual-Layer Cooperative Error Control for Reliable Nanoscale On-Chip Interconnection Networks
    • 批准号:
      0925993
    • 项目类别:
      Standard Grant
    • 资助金额:
      $29.01万
    • 财政年份:
      2009
    • 负责人:
      Paul Ampadu
    • 依托单位:
    Reliable Backend Integrated Hybrid Photonic-Electronic Network-on-Chip
    • 批准号:
      0903448
    • 项目类别:
      Standard Grant
    • 资助金额:
      $53.0万
    • 财政年份:
      2009
    • 负责人:
      Paul Ampadu
    • 依托单位:
    SGER: Investigating the Turbo Principle for Reliable Energy-Efficient Networks-on-Chip
    • 批准号:
      0733450
    • 项目类别:
      Standard Grant
    • 资助金额:
      $0.0万
    • 财政年份:
      2007
    • 负责人:
      Paul Ampadu
    • 依托单位:
    国内基金
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      82371765
    • 项目类别:
      面上项目
    • 资助金额:
      50万元
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      2023
    • 负责人:
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    • 批准号:
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    • 项目类别:
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    鼠伤寒沙门氏菌LPS core经由CD209/SphK1促进树突状细胞迁移加重炎症性肠病的机制研究
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