Reliable Backend Integrated Hybrid Photonic-Electronic Network-on-Chip

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The objective of this research is to create a reliable hybrid photonic-electronic network-on-chip for high performance multicore chips. This is achieved through backend integration of a silicon-compatible nanophotonic optical network configured and monitored using an electronic packet-switched network.Intellectual Merit: Metal interconnects have emerged as the critical bottleneck in meeting reliability, performance and energy constraints in chip multiprocessors. Silicon nanophotonics offers a compelling alternative, because of its inherently large bandwidth, low loss, low energy consumption and CMOS compatibility. This research addresses barriers challenging the efficient and cost-effective integration of on-chip photonic networks by (1) investigating CMOS compatible fabrication of amorphous silicon nanophotonic components for maximum backend flexibility; (2) examining scalable architectures, topologies and routing mechanisms for these photonic-electronic on-chip networks; (3) exploring error control methods for reliable energy-efficient multicore communication; (4) developing robust low-jitter mode-locked quantum-dot lasers that supply light to the photonic network.Broader Impact: Successful demonstration of the hybrid photonic-electronic network-on-chip will accelerate realization of reliable energy efficient data-centers and high performance computational systems for a multitude of societal applications. Integration of research and education builds on the PIs' own community involvement and excellent campus-wide resources offered by the participating universities to (1) train the next generation of scholars through a joint course to be developed by the PIs and planned workshops that enable student participants to interact with experts; (2) actively recruit and mentor qualified underrepresented students; (3) inspire participation of K-12 groups through hands-on laboratory activities; (4) extend outreach through international collaborations.