Dual-Layer Cooperative Error Control for Reliable Nanoscale On-Chip Interconnection Networks

本研究的目的是研究适用于奈米级芯片网络的能量高效的双层(数据链路层和网络层)协同差错控制方法。该方法将数据链路层的逐跳错误检测与网络层的自适应路由和端到端前向纠错相结合，在智能方面解决了以下问题：随着技术的积极扩展，互连变得越来越容易受到噪声的影响，成为满足纳米级片上系统可靠性和能量约束的关键瓶颈。对可靠互连的研究通常在单层(例如，物理或电气)上调查解决方案。本研究结合网络层前向纠错的可靠性性能，综合考虑交换级差错检测的硬件效率和网络层前向纠错的可靠性，以同时提高可靠性和能耗为目标。具体地说，这项研究旨在：(I)创建新的高效代码用于片上网络中跨层的错误检测和纠正；(Ii)设计创新的方法，使用可配置的备用线和自适应布线来管理间歇性和永久性错误；以及(Iii)研究和开发减轻编解码器电路自身故障影响的方法。从更广泛的影响来看，本研究具有创建一种新的可靠互连设计方法的潜力，可以加速可扩展多核片上系统的进步。这一突破可能会产生重大的社会和经济影响，为从基础设施监测到卫生保健的各种应用实现可靠的节能综合系统。所产生的知识通过讲习班、讲座和公共网站传播。这项研究积极接触代表不足的少数族裔和女性学生，并通过国际合作扩大范围，以拓宽美国学生的全球视野。

The objective of this research is to investigate energy-efficient cooperative dual-layer (data link and network layers) error control methods for nanoscale networks-on-chip. The approach is to combine hop-to-hop error detection at the data link layer with adaptive routing and end-to-end forward error correction at the network layer.With respect to intellectual merit, this research addresses the problem that, with aggressive technology scaling, interconnects become increasingly susceptible to noise and they emerge as the critical bottleneck in meeting reliability and energy constraints in nanoscale systems-on-chip. Research in reliable interconnects has typically investigated solutions at a single layer, e.g. physical or electrical. This research considers the hardware efficiency of switch-level error detection combined with the reliability performance of network-layer forward error correction, with the goal of simultaneously improving reliability and energy use. In particular, this research seeks to: (i) create new efficient codes for error detection and correction across layers in a network-on-chip; (ii) devise innovative methods, using configurable spare wires and adaptive routing, to manage intermittent and permanent errors; and (iii) examine and develop methods to mitigate the impact of faults in the encoder/decoder circuits themselves.With respect to broader impact, this research has the potential to create a new reliable interconnect design approach that can accelerate advances in scalable multi-core systems-on-chip. This breakthrough could have significant societal and economic impact with the realization of reliable energy-efficient integrated systems for numerous applications, ranging from infrastructure monitoring to health care. Knowledge generated is disseminated through workshops, lectures and a public website. This research actively engages underrepresented minority and female students and extends outreach through international collaborations to broaden the global perspectives of U.S. students.