Dual-Layer Cooperative Error Control for Reliable Nanoscale On-Chip Interconnection Networks

本研究的目的是探讨纳米级片上网络的节能合作双层（数据链路和网络层）误差控制方法。该方法将数据链路层的跳到跳错误检测与网络层的自适应路由和端到端前向错误校正相结合。在知识价值方面，本研究解决了这样一个问题，即随着积极的技术扩展，互连变得越来越容易受到噪声的影响，并且它们成为满足纳米级片上系统可靠性和能量限制的关键瓶颈。对可靠互连的研究通常是研究单层的解决方案，例如物理或电气。本研究将交换机级错误检测的硬件效率与网络层前向纠错的可靠性性能相结合，以同时提高可靠性和能耗。特别是，本研究旨在：(i)在片上网络中创建新的有效代码，用于跨层的错误检测和纠正；（ii）设计创新方法，使用可配置的备用电线和自适应布线，以管理间歇性和永久性错误；（iii）检查和开发方法，以减轻编码器/解码器电路本身故障的影响。就更广泛的影响而言，这项研究有可能创造一种新的可靠的互连设计方法，可以加速可扩展的多核片上系统的发展。这一突破可能会对社会和经济产生重大影响，为从基础设施监测到医疗保健等众多应用实现可靠的节能综合系统。所产生的知识通过讲习班、讲座和公共网站传播。这项研究积极吸引代表性不足的少数民族和女学生，并通过国际合作扩大外展范围，拓宽美国学生的全球视野。

The objective of this research is to investigate energy-efficient cooperative dual-layer (data link and network layers) error control methods for nanoscale networks-on-chip. The approach is to combine hop-to-hop error detection at the data link layer with adaptive routing and end-to-end forward error correction at the network layer.With respect to intellectual merit, this research addresses the problem that, with aggressive technology scaling, interconnects become increasingly susceptible to noise and they emerge as the critical bottleneck in meeting reliability and energy constraints in nanoscale systems-on-chip. Research in reliable interconnects has typically investigated solutions at a single layer, e.g. physical or electrical. This research considers the hardware efficiency of switch-level error detection combined with the reliability performance of network-layer forward error correction, with the goal of simultaneously improving reliability and energy use. In particular, this research seeks to: (i) create new efficient codes for error detection and correction across layers in a network-on-chip; (ii) devise innovative methods, using configurable spare wires and adaptive routing, to manage intermittent and permanent errors; and (iii) examine and develop methods to mitigate the impact of faults in the encoder/decoder circuits themselves.With respect to broader impact, this research has the potential to create a new reliable interconnect design approach that can accelerate advances in scalable multi-core systems-on-chip. This breakthrough could have significant societal and economic impact with the realization of reliable energy-efficient integrated systems for numerous applications, ranging from infrastructure monitoring to health care. Knowledge generated is disseminated through workshops, lectures and a public website. This research actively engages underrepresented minority and female students and extends outreach through international collaborations to broaden the global perspectives of U.S. students.