SBIR Phase I: Creating Delay-tolerant, Asynchronous Network Interfaces

这个小型企业创新研究 (SBIR) 第一阶段项目解决了集成电路 (IC) 片上系统 (SoC) 产品中日益严重的问题。每个这样的产品可能有数十亿个晶体管，并且特征尺寸小于可见光的波长。由于晶体管可变性显着增加以及需要大幅降低功耗，现代半导体工艺给 IC 制造带来了新的挑战。 Blendics 开发了一种包装技术，使每个 SoC 子系统看起来就像是异步的并且独立于其邻居，从而减少参数变化的不良影响并实现动态功耗降低技术。然而，对这些包装器使用手动设计方法是不够的。这项研究的目标是使该设计任务自动化，使这些包装机的广泛使用在经济上具有吸引力，并且仍然能够克服不可避免的过程可变性挑战。所提出的研究融合了异步和同步设计技术，以保留传统工具的优点，同时避免其缺点。结果将是一个设计自动化工具，可以根据其电路规范生成子系统的包装器。如果该工具能够以最少的设计人员额外工作量为各种子系统生成包装器，则将取得成功。该项目更广泛的影响/商业潜力源于以下事实：SoC 技术可用于电话、娱乐产品、医疗保健设备、汽车设备、计算机和现代生活中丰富的许多其他应用。单个 SoC 的生产成本可能非常低廉，但目前设计和制造第一个高级定制 SoC 的成本约为 8500 万美元。随着新的半导体工艺的引入，这种成本必然会上升。大部分设计成本与克服与子系统之间的全局连接相关的时序限制有关。这就是所提出的包装器技术要解决的问题。因此，制定用于创建片上网络的全球标准对于价值 1.7B 美元的硅知识产权业务领域来说是一个重大机遇。这样的标准可以克服半导体行业在发展过程中面临的严重技术问题。如果没有良好的解决方案来解决工艺可变性问题，SoC 的第一个副本的成本可能会变得如此之高，以至于只有最高产量的产品才能具有良好的商业意义。因此，公众可能无法访问医疗和安全应用中的重要 SoC 产品。

This Small Business Innovation Research (SBIR) Phase I project addresses a growing problem in integrated circuit (IC) system-on-chip (SoC) products. Each such product may have billions of transistors and a feature size of less than the wavelength of visible light. Modern semiconductor processes bring new challenges to IC fabrication because of significantly increased transistor variability and the need to greatly reduce power dissipation. Blendics has developed a wrapper technology that makes each SoC subsystem appear as if it were asynchronous and independent of its neighbors, thereby reducing the undesirable effects of parameter variability and enabling dynamic power reduction techniques. However, the use of manual design methods for these wrappers is inadequate. The goal of this research is to automate this design task making the widespread use of these wrappers economically attractive and still capable of overcoming the inevitable process variability challenges. The proposed research blends asynchronous and synchronous design techniques in order to retain the advantages of conventional tools while avoiding their disadvantages. Results will be a design-automation tool that generates a subsystem?s wrapper from its circuit specification. Success will be achieved if this tool generates wrappers for a broad variety of subsystems with a minimum of additional designer effort.The broader impact/commercial potential of this project arises from the fact that SoC technology finds use in phones, entertainment products, health-care devices, automotive equipment, computers and many other applications that abound in modern life. An individual SoC may be seductively inexpensive in production, but the cost to design and fabricate the first copy of an advanced, custom SoC is today approximately $85 million US dollars. This cost is bound to rise as new semiconductor processes are introduced. Much of this design cost is associated with overcoming the timing constraints associated with global connectivity among the subsystems. This is the problem that the proposed wrapper technology addresses. Thus, developing a world-wide standard for creating a network-on-chip is a significant opportunity in the $1.7B silicon intellectual-property business sector. Such a standard could overcome the serious technical problem the semiconductor industry faces as it moves forward. In the absence of a good solution to this problem of process variability, the cost of the first copy of an SoC is likely to become so high that only the highest volume products will make good business sense. As a result, public access may be denied important SoC products in medical and safety applications.