Asynchronous Nanowire Reconfigurable Crossbar Architecture for Manufacturability, Scalability, Robustness and Defect & Fault-Tolerance

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The objective of this research is to develop novel asynchronous nanowire crossbar architecture to address various design and manufacturing issues with conventional clocked counterpart. The approach is based on a delay-insensitive encoding and handshaking technique known as Null Convention Logic (NCL). Intellectual Merit:By enabling separation between control and data representations, the proposed architecture provides self-synchronization throughout the design. No clock distribution network needs to be fabricated along with nanowire crossbars. Also numerous timing-related failure modes and parametric variations caused by nondeterministic nanoscale assembly can be intrinsically tolerated. Since all timing information is embedded in the encoding and locally handled, the timing complexity remains the same even though the size of the circuit to be programmed increases. Therefore, potential benefits from the proposed clock-free nanowire crossbar architecture include improved manufacturability, scalability, modularity and robustness.Broader Impact:Results and findings from the proposed research will be helpful to break the photolithographic limit; high-density nanowire crossbar-based computing systems, which are more manufacturable, scalable and robust, can be easily realized by the proposed asynchronous architecture. The results of the project will be actively disseminated by scientific papers, software and online demos, which can be accessed from the project website and NANOHUB.ORG. This project will also include a major component of research and education activities for undergraduates and under-represented minorities and interdisciplinary research collaboration with industrial partner.