CPA-CSA-T: Arsenal: Extending Moore's Law through the Design, Synthesis and Use of Massively Heterogeneous Systems

点击翻译按钮获取中文摘要

Power and microarchitectural scalability concerns have motivated the recent industrial transition to multicore processors. In the near future, because of VLSI scaling limitations, processors will only be able to make use of a small fraction of the die at one time at full speed. The emergence of three-dimensional CMOS integration exacerbates this problem by substantially increasing device count without improving transistor power efficiency. This "utilization wall" threatens to halt the progress of Moore's law and stop the yearly improvements in processor performance that have transformed society over the last 40 years. This research attacks the utilization wall by examining the design, construction and analysis of Arsenal processors. Arsenal processors are comprised of a heterogeneous array of 10s to 100s to even 1000s of specialized processing elements (SPEs), a small subset of which will be active at any time. The SPEs in an Arsenal system will vary from specialized ASICs to graphics accelerators and out-of-order superscalars. Different parts of a program will run on the SPEs best suited to each part. Since specialized processors are generally smaller and more efficient, each program will use just a fraction of the die, but will do so extremely efficiently. Our preliminary results show that Arsenal designs improve power efficiency by up to 7x compared to less aggressively heterogeneous approaches. While the potential benefits of Arsenal-style processors are alluring, Arsenal systems present significant challenges as well. Designers must find a way to quickly develop a wide range of SPEs that can collectively improve efficiency for a typical end-user's workload. The memory system in an Arsenal design must deliver sufficient memory bandwidth to each SPE.Arsenal processors must include an on-chip interconnect that can support thousands of communicating SPEs. To this end, we will colloborate with the MIT ATAC project, which focuses on on-chip interconnect design, and we will incorporate their interconnect into our own work. The proposed work will explore many architectural challenges that arise in designing massively heterogeneous Arsenal systems with potentially 1000s of specialized cores. Its goals are to demonstrate the potential of Arsenal processors, develop the tools needed to design complete Arsenal-based systems, and to build a complete, general-purpose prototype Arsenal processor.