CPA-DA: A 3D CMP-aware Nanoscale IC Design Methodology using Physics-based Modeling with Silicon Validation via Test and Diagnosis

提案ID: 0811770PI：希格斯，塞西尔f .机构：卡耐基梅隆大学标题：三维cmp感知纳米级IC设计方法使用基于物理的建模与硅验证通过测试和诊断摘要是众所周知的？摩尔?法律?由于技术进步，计算机芯片的速度几乎每两年就会翻一番。这一进步通常是由于芯片上晶体管的尺寸正在迅速缩小到一纳米（比人类头发细1000倍）。由于晶体管更小，更多的晶体管可以放在一个芯片上，从而提高计算速度。不幸的是，制造这些计算机芯片的过程非常复杂，最终产品往往会出现缺陷或性能低于原始设计。一种特殊的制造工艺，化学机械抛光（CMP），是性能下降和制造成本的主要贡献者。通过将芯片缺陷测试模型与先进的CMP计算机模型相结合，主要研究人员（pi）建议研究和开发一种突破性的计算方法，用于预测CMP制造过程在设计阶段对芯片的影响。CMP是一个复杂的过程，通过将包含芯片的晶圆表面压在一个旋转垫上进行抛光，该旋转垫充满了由含有研磨性纳米颗粒的流体组成的浆液。为了准确地模拟这一过程，必须通过电子和计算机工程、应用物理学和机械工程的合作研究来开发复杂的计算机模型。这项研究产生的预测计算工具将从根本上改善并行工程，芯片设计人员可以创建更大胆的设计，因为他们将意识到CMP对其布局的影响。由此产生的影响将是更复杂的计算机芯片设计，利用最先进的材料，由于CMP对材料的影响的不确定性，通常可以避免这种情况。由于pi持续参与少数民族学生的招募和教育，这项工作也将提供许多机会来了解美国。为美国大学预科和大学阶段的下一代工程专业学生提供半导体技术前沿研究的机会。

PROPOSAL ID: 0811770PI: HIGGS, CECIL F.INSTITUTION: CARNEGIE-MELLON UNIVERSITYTITLE: A 3D CMP-AWARE NANOSCALE IC DESIGN METHODOLOGY USING PHYSICS-BASED MODELING WITH SILICON VALIDATION VIA TEST AND DIAGNOSISABSTRACTIt is well known that ?Moore?s Law? states that computer chips will double their speed nearly every two years due to technological advancement. This advancement is typically due to the size of the transistors on the chip which are rapidly becoming as small as a nanometer (which is 1000 times thinner than a human hair). Since the transistors are smaller, more of them can be put on a chip which leads to faster computational times. Unfortunately, the processes needed to manufacturing these computer chips are highly complex and the final product often comes out defective or with lower performance than the original design. One particular manufacturing process, chemical mechanical polishing (CMP), is a major contributor to performance degradation and manufacturing costs. By combining chip defect testing models with advanced CMP computer models, the principal investigators (PIs) propose to research and develop a breakthrough computational methodology for predicting the impact of the CMP manufacturing process on the chip at the design stage. CMP is a complex process in which the wafer surface that contains the chips is polished by pressing it against a rotating pad that is flooded with a slurry consisting of a fluid with abrasive nanoparticles. In order to accurately model this process, sophisticated computer models must be developed through collaborative research at the interface of electrical and computer engineering, applied physics, and mechanical engineering. A predictive computational tool resulting from this research would lead to radically improved concurrent engineering where chip designers are enabled to create bolder designs since they would be aware of the ramifications of CMP on their layouts. The resulting impact would be more sophisticated computer chip designs that exploit the most advanced materials which might normally be avoided due to the uncertainty of the effect of CMP on the materials. Due to the PIs on-going involvements with the recruitment and education of minority students, this work will also provide numerous opportunities to expose America?s next generation of engineering students at the pre-college and college levels to cutting-edge research in semiconductor technologies.