CPA-DA: A 3D CMP-aware Nanoscale IC Design Methodology using Physics-based Modeling with Silicon Validation via Test and Diagnosis

提案ID：0811770PI：Higgs，Cecil F.Instittion：Carnegie-Mellon UNIVERSITYTLE：一种基于物理建模的3D CMP纳米级IC设计方法，通过测试和诊断进行硅验证。众所周知，摩尔？S定律？由于技术的进步，计算机芯片的速度几乎每两年就会翻一番。这种进步通常归功于芯片上晶体管的大小，这些晶体管正迅速变得小到一纳米(比人的头发还细1000倍)。由于晶体管更小，更多的晶体管可以放在芯片上，从而导致更快的计算时间。不幸的是，制造这些计算机芯片所需的工艺非常复杂，最终产品往往是有缺陷的，或者性能低于原始设计。一种特殊的制造工艺，化学机械抛光(CMP)，是导致性能下降和制造成本的主要因素。通过将芯片缺陷测试模型与先进的化学机械抛光计算机模型相结合，首席研究人员(PI)建议研究和开发一种突破性的计算方法，以便在设计阶段预测化学机械抛光制造工艺对芯片的影响。化学机械抛光是一个复杂的过程，在这个过程中，包含芯片的晶片表面通过将其压在旋转衬垫上进行抛光，旋转衬垫充满了由含有研磨性纳米颗粒的流体组成的浆液。为了准确地模拟这一过程，必须通过在电气和计算机工程、应用物理和机械工程的界面上进行协作研究来开发复杂的计算机模型。这项研究产生的预测性计算工具将从根本上改进并行工程，使芯片设计者能够创建更大胆的设计，因为他们将意识到CMP对他们布局的影响。由此产生的影响将是利用最先进材料的更复杂的计算机芯片设计，这通常是可以避免的，因为化学机械抛光对材料的影响不确定。由于PIS正在不断地参与少数族裔学生的招生和教育，这项工作也将提供大量机会，让美国S下一代大学预科和大学阶段的工程专业学生接触到半导体技术的尖端研究。

PROPOSAL ID: 0811770PI: HIGGS, CECIL F.INSTITUTION: CARNEGIE-MELLON UNIVERSITYTITLE: A 3D CMP-AWARE NANOSCALE IC DESIGN METHODOLOGY USING PHYSICS-BASED MODELING WITH SILICON VALIDATION VIA TEST AND DIAGNOSISABSTRACTIt is well known that ?Moore?s Law? states that computer chips will double their speed nearly every two years due to technological advancement. This advancement is typically due to the size of the transistors on the chip which are rapidly becoming as small as a nanometer (which is 1000 times thinner than a human hair). Since the transistors are smaller, more of them can be put on a chip which leads to faster computational times. Unfortunately, the processes needed to manufacturing these computer chips are highly complex and the final product often comes out defective or with lower performance than the original design. One particular manufacturing process, chemical mechanical polishing (CMP), is a major contributor to performance degradation and manufacturing costs. By combining chip defect testing models with advanced CMP computer models, the principal investigators (PIs) propose to research and develop a breakthrough computational methodology for predicting the impact of the CMP manufacturing process on the chip at the design stage. CMP is a complex process in which the wafer surface that contains the chips is polished by pressing it against a rotating pad that is flooded with a slurry consisting of a fluid with abrasive nanoparticles. In order to accurately model this process, sophisticated computer models must be developed through collaborative research at the interface of electrical and computer engineering, applied physics, and mechanical engineering. A predictive computational tool resulting from this research would lead to radically improved concurrent engineering where chip designers are enabled to create bolder designs since they would be aware of the ramifications of CMP on their layouts. The resulting impact would be more sophisticated computer chip designs that exploit the most advanced materials which might normally be avoided due to the uncertainty of the effect of CMP on the materials. Due to the PIs on-going involvements with the recruitment and education of minority students, this work will also provide numerous opportunities to expose America?s next generation of engineering students at the pre-college and college levels to cutting-edge research in semiconductor technologies.