Collaborative Research: CPA-CSA: CMP Architecures with Global Communication

本提案的重点是评估使用瞬时，芯片范围的全球信息，以提高性能，降低功耗和成本，在大规模，芯片多处理器（CMP）。 使用全局信息与传统思想相矛盾，因为已经假设遍历整个芯片需要许多时钟周期。 然而，最近开发的电路使单周期，芯片范围的信号，提出了新的可能性，结合全球和本地信息同时进行。 此外，类似的想法还没有实现在大型的，传统的多芯片系统，因为设计的灵活性，互连可配置性，和晶体管性能的改善只存在于chip.Preliminary探索已确定所需的互连电路和硬件和软件的机会，以利用最新的全球信息。该研究计划利用新的电路技术，使拟议的片上网络（NOC）与混合互连（NOCHI）架构，它既有一个数据平面使用传统的互连技术和超低延迟控制平面与全球互连。由于NOCHI忽略了已建立的设计模式，因此了解电路特性对于架构研究至关重要，这些研究包括：可以更好地控制和调节网络内和跨核功耗的新算法;改进核与片外存储器系统的交互以减少对片上网络资源的需求;全局信息对高速缓存一致性和管理的影响;以及软件控制的超低延迟高效多核同步。

The focus of this proposal is to evaluate the use of instantaneous, chip-wide global information for increasing performance and reducing power and cost in large-scale, chip multi-processors (CMPs). Using global information contradicts conventional thinking because it has been assumed that traversing the entire chip requires many clock periods. Recently developed circuits, however, enable single-cycle, chip-wide signaling, suggesting new possibilities of combining global and local information simultaneously. Further, similar ideas have not been previously implemented in large, traditional multi-chip systems because design flexibility, interconnect configurability, and transistor performance improvements exist only on chip.Preliminary exploration has identified both the required interconnect circuits and opportunities for hardware and software to take advantage of up-to-date global information. The research plans to exploit new circuit techniques that will enable the proposed network-on-chip (NOC)with hybrid interconnect (NOCHI) architecture, which has both a data plane using conventional interconnect techniques and an ultra low-latency control plane with a global interconnect. Because NOCHI ignores established design patterns, understanding the circuit properties is essential for the architectural studies, which include: new algorithms that can better control and regulate power consumption within the network and across cores; improved interaction of the cores with the off-chip memory system to reduce demands on on-chip network resources; the ramifications of global information on cache coherence and management; and software controlled, ultra low-latency efficient synchronization for multicores.