CPA-CPL: Cache-Aware Synchronization and Scheduling of Data-Parallel Programs for Multi-Core Processors

CPA-CPL：多核处理器数据并行程序的缓存感知同步和调度

• 批准号: 0811882
• 负责人: Alexander Veidenbaum
• 金额: $ 29.87万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811882&HistoricalAwards=false
• 关键词: CPA; CPL; Cache; Aware; Synchronization

Project AbstractMulti-core (parallel) processors are becoming ubiquitous. The use of such systems is key to science, engineering, finance, and other major areas of the economy. However, increased applications performance on such systems can only be achieved with advances in mapping such applications to multi-core machines. This task is made more difficult by the presence of complex memory organizations which is perhaps the key bottleneck to efficient execution, and which was not previously addressed effectively. This research involves making the mapping of the program to the machine aware of the complexities of the memory-hierarchy in all phases of the compilation process. This will ensure a good fit between the application code and the actual machine and thereby guarantee much more effective utilization of the hardware (and thus efficient/fast execution) than was previously possible. Modern processors (multi-cores) employ increasingly complex memory hierarchies. Management of such hierarchies is becoming critical to the overall success of the compilation process since effective utilization of the memory hierarchy dominates overall performance. This research develops a new cache-hierarchy-aware compilation and runtime system (i.e., including compilation, scheduling, and static/dynamic processor mapping of parallel programs). These tasks have one thing in common: they all need accurate estimates of data element (iteration, task) computation and memory access times which are currently beyond the (cache-oblivious) state-of-the-art. This research thus develops new techniques for iteration space partitioning, scheduling, and synchronization which capture the variability due to cache, memory, and conditional statement behavior and their interaction. This research will have a broad impact on the computer industry as it will allow the ubiquitous multi-core systems of the future to be efficiently exploited by parallel programs.

项目摘要多核（并行）处理器正在变得无处不在。这些系统的使用是科学、工程、金融和其他主要经济领域的关键。然而，只有在将这些应用程序映射到多核机器方面取得进展的情况下，才能在这些系统上实现更高的应用程序性能。复杂的内存组织的存在使得这项任务变得更加困难，这可能是高效执行的关键瓶颈，并且以前没有有效地解决。 这项研究涉及到使映射的程序到机器知道的复杂性的内存层次结构在编译过程的所有阶段。这将确保应用程序代码和实际机器之间的良好匹配，从而保证比以前更有效地利用硬件（从而有效/快速执行）。现代处理器（多核）采用越来越复杂的内存层次结构。这种层次结构的管理对于编译过程的整体成功变得至关重要，因为存储器层次结构的有效利用主导了整体性能。本研究开发了一种新的缓存层次感知编译和运行时系统（即，包括并行程序的编译、调度和静态/动态处理器映射）。这些任务有一个共同点：他们都需要准确估计的数据元素（迭代，任务）的计算和内存访问时间，这是目前超出（高速缓存不经意）的最先进的。因此，这项研究开发了新的技术迭代空间划分，调度和同步捕获的变化，由于高速缓存，内存和条件语句的行为和它们的相互作用。这项研究将对计算机行业产生广泛的影响，因为它将允许并行程序有效地利用未来无处不在的多核系统。