SHF: Small: Improving single core performance via compiler-assisted out-of-order commit

SHF：小：通过编译器辅助的乱序提交提高单核性能

• 批准号: 1118047
• 负责人: Alexander Veidenbaum
• 金额: $ 29.88万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1118047&HistoricalAwards=false
• 关键词: SHF; Small; Improving; single; core

The performance growth in uniprocessor (single core) performance resulting from improvements in semiconductor technology has recently slowed down significantly. Sequential applications or sequential portions of parallel applications require further advances to improve their performance. Today's processors complete instructions in their program order, which is a major performance bottleneck because any long-latency instruction, such as access to memory, delays completion of all subsequent instructions. This project aims to achieve higher single core performance by defining a new, compiler assisted mechanism for out of order instruction completion. It investigates how the use of compile-time program knowledge can be passed to the hardware and be used to simplify the architectural checks required for such out of order completion. The architecture of a standard processor is fully preserved and legacy software can execute without modification.The out-of-order instruction commit mechanism will use a novel compiler/architecture interface. The compiler provides information about instruction ``blocks'' and the processor uses the block information to decide which instructions can be committed out of order and when. Some blocks are guaranteed to be data independent blocks which allows instructions from different such blocks be committed simultaneously and out of order. Other blocks have data or control dependencies and require in-order execution and in-order commit. Micro-architectural support for the new commit mode is driven by the block information, which significantly simplifies the hardware. Exception handling is also simplified with compiler assistance. The new commit mechanism will effectively increase the size of the instruction window allowing more cache misses to be overlapped for both L1 and L2 caches. The project will also investigate additional compiler and architecture optimizations to further improve performance.

由于半导体技术的改进，单处理器(单核)性能的性能增长最近显着放缓。顺序应用程序或并行应用程序的顺序部分需要进一步改进以提高其性能。如今的处理器按程序顺序完成指令，这是一个主要的性能瓶颈，因为任何长延迟指令，如访问存储器，都会推迟所有后续指令的完成。该项目旨在通过定义一种新的、编译器辅助的乱序指令完成机制来实现更高的单核性能。它研究如何将编译时程序知识的使用传递到硬件，并用于简化这种无序完成所需的体系结构检查。标准处理器的体系结构被完全保留，遗留软件无需修改即可执行。无序指令提交机制将使用新的编译器/体系结构接口。编译器提供有关指令“块”的信息，处理器使用块信息来决定哪些指令可以无序提交以及何时提交。一些块被保证是数据独立的块，这允许来自不同这样的块的指令被同时无序地提交。其他块具有数据或控制依赖关系，需要按顺序执行和按顺序提交。对新提交模式的微体系结构支持由块信息驱动，这显著简化了硬件。在编译器的帮助下，异常处理也得到了简化。新的提交机制将有效地增加指令窗口的大小，从而允许L1和L2高速缓存的更多高速缓存未命中重叠。该项目还将调查其他编译器和架构优化，以进一步提高性能。