CSR-PSCE,SM: A Holistic Design Approach to Reliability Using 3D Stacked
CSR-PSCE,SM: A Holistic Design Approach to Reliability Using 3D Stacked
批准号:
0834798
负责人:
Murali Annavaram
金额:
$40.29万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2008
资助国家:
美国
项目状态:
已结题
起止时间:
2008-09-01 至 2013-08-31
中文摘要
信息技术产业的未来取决于设计出能够容忍由设备特性变化引起的错误的计算机系统。传统上,系统可靠性是通过复制关键系统组件来实现的。由于可变性引起的错误随着时间的推移缓慢发生,因此仅以提供可靠性为目的的复制对于低成本计算平台来说是非常昂贵的。本研究探索使用3D堆叠在3D堆叠晶片上实现冗余元件和可变性监测电路。使用3D堆叠,冗余计算块可以使用可变弹性处理技术构建,该技术可能比用于构建主处理器的处理技术慢。本研究采用整体方法设计3D堆叠监控,从创新的微架构解决方案到利用应用程序固有的容错能力。在微架构方面,本研究探索了无缝重新配置监控层的潜力,使其在三种模式下发挥作用:当可变性引起的错误很少时,作为性能辅助;当可变性引起的错误开始出现时,作为保护处理器;当设备老化可能导致主处理基板上出现不可修复的错误时,作为备份处理器。在架构方面,本研究探索了一种新的异常类,称为可靠性感知异常,它允许微架构块在响应可变性引起的错误时引发异常。然后,应用程序类可以利用这些软件可见异常,这些应用程序类具有固有的容错性,并且可以自定义异常处理机制。
英文摘要
The future of information technology industry depends on designing computer systems that are tolerant of errors caused by variations in device characteristics. Traditionally system reliability is achieved by replicating critical system components. Since variability induced errors occur slowly over time, replication for the sole purpose of providing reliability is prohibitively expensive for low cost computing platforms. This research explores using 3D stacking to implement redundant components and variability monitoring circuitry on a 3D stacked die. Using 3D stacking the redundant computation blocks can be built using a variation resilient process technology that may be slower than the process technology used for building the primary processor. This research takes a holistic approach to designing the 3D stacked monitoring spanning from innovative microarchitecture solutions to exploiting application's inherent error tolerance. On the microarchitecture front, this research explores the potential for seamlessly reconfiguring the monitoring layer to act in three modes: performance assists, when variability induced errors are rare, or as guard processors, when variability induced errors begin to appear, or as backup processors, when device aging may result in irreparable errors on the primary processing substrate. On the architecture front, this research explores a new exception class called Reliability Aware Exceptions that allow microarchitecture blocks to raise an exception in response to a variability induced error. These software visible exceptions can then be exploited by application classes that are inherently error tolerant and can customized exception handling mechanisms.
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