CSR-PSCE,SM: Trade-offs Between Static Power, Performance and Reliability in Future Chip Multiprocessors

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As the transistor growth outpaced the design and verification effort in chip design, a large fraction of on-chip transistors are now allocated to storage structures, such as caches. The static power consumed by these storage structures worsen the critical problems of power and thermal issues faced by current chip designs. To reduce the static power, drowsy techniques are used, where inactive components of a storage structure can be placed in a low power state. Unfortunately, drowsy power states increase the susceptibility of transistors to transient errors. Motivated by these problems, this research explores the tradeoffs between static power, performance and reliability in chip multiprocessors. The fundamental contribution of this research is to develop a novel hybrid analytical/simulation framework that allows designers to evaluate the impact of reducing static power on processor reliability and performance. Using this framework this research explores new cache management and cache protocols in chip-multiprocessors and the impact of these new schemes on reliability and performance of a computer system. The framework can also be extended to analyze the power, performance and reliability tradeoffs of other storage structures inside each core such as the reorder buffer, the branch prediction tables, and various instruction and scheduling queues.