CSR-PSCE, SM: Memory Management Innovations for Next-Generation SMP

多核计算的引入带来的并行编程的潜在范式转变以及由此带来的挑战才刚刚开始被消费者和程序员所体验。一个最重要的挑战是可伸缩性，特别是在日益广泛的自动化内存管理技术，如垃圾收集。随着架构向80核及以上发展，需要几乎不需要同步和共享状态的新算法。所谓的“无锁”算法利用原子低级硬件指令，这些指令要么非常昂贵，要么由于高速缓存一致性和存储器模型约束而表现出次线性可扩展性。这个项目提出了三个贡献，为程序员简化了并行系统中固有的复杂性，同时提供了保护，死锁、活锁、数据竞争以及零日漏洞等安全威胁。这些贡献包括（1）Ribbons -一种新的、更灵活的共享内存编程模型，其中可以在受限线程之间以成对的方式指定共享约束。Ribbons可以防止对数据的无意或恶意访问，并减少不安全运行时环境中的无限堆损坏，并支持熟悉的线程模型。(2)自动化内存管理技术，在32核及以上的核上表现出接近线性的加速。这些技术主要包括利用线程本地数据的垃圾收集方案，以避免快速路径中代价高昂的原子指令。操作系统级别的集成支持。前两个目标可以单独执行，但在各级合并为一个单一系统时会产生许多协同作用。在操作系统的集成支持将导致更多的可扩展性，能源意识的任务调度算法，并将提供所需的新的基本执行模型的ribbon在行业中可行，并成为广泛采用的系统范围内的支持。该项目建议与社区合作，以加强现有的内存管理基准，以适当地测试跨32+核心的可扩展性。评估阶段还将涉及一个案例研究，本科生使用丝带或正常的线程和过程来实现一个项目。 该项目中实现的所有软件都将在开源许可证下提供。

The underlying paradigm shift to parallel programming brought on by the introduction of multicore computing and the resulting challenges posed by this shift are just beginning to be experienced by consumers and programmers alike. A foremost challenge is scalability, especially in increasingly widespread automated memory management techniques such as garbage collection. As architectures move to 80 cores and beyond, new algorithms are needed that require almost zero synchronization and shared state. So-called "lock-free" algorithms leverage atomic low-level hardware instructions which are either quite expensive or exhibit sub-linear scalability due to cache coherency and memory-model constraints.To pave the way for exploiting the potential of future scalable symmetric multiprocessing (SMP) this project proposes three contributions that simplify the inherent complexity within parallel systems for programmers and at the same time offering protection from deadlocks, livelocks, data races, as well as from security threats such as zero-day exploits. These contributions include (1) Ribbons - a new, more flexible, shared-memory programming model, where sharing constraints can be specified in a pair-wise fashion between restricted threads. Ribbons protect against inadvertent or malicious access to data and mitigate unbounded heap corruption in unsafe runtime environments, and subsume the familiar thread model. (2) Automated memory management techniques that exhibit near linear speedups on 32 cores and beyond. These techniques primarily consist of a garbage collection scheme that exploits thread-local data to avoid costly atomic instructions in the fast path. (3). Integrated support at the OS level. The two previous goals can be implemented in isolation, but exhibit many synergies when combined into a single system at all levels. Integrated support at the OS will lead to more scalable, energy-aware task scheduling algorithms and will provide the systemic-wide support required for the new fundamental execution model of ribbons to be viable in industry and become widely adopted.This project proposes cooperation with the community to enhance existing memory management benchmarks to suitably test scalability across 32+ cores. The evaluation stage will also involve a case study where undergraduate students implement a project using either ribbons or normal threads and processes. All software implemented in this project will be made available under open source licenses.