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CAREER: Rotary Clock Technology Integration

CAREER: Rotary Clock Technology Integration
职业:旋转时钟技术集成
批准号:
0845270
负责人:
Baris Taskin
金额:
$40.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-09-15 至 2014-08-31

项目摘要

项目成果

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中文摘要
翻译
该奖项是根据2009年《美国复苏和再投资法案》(Public Law 111-5)资助的。实现低功耗的高质量同步是高频同步VLSI电路设计的主要目标。为了达到这一目标,传统的时钟设计方法正在不断改进。此外,传统时钟的下一代替代方案也在不断涌现。谐振时钟技术提供的工作频率和功耗水平在最先进的体积型CMOSVLSI集成电路实现中是前所未有的。这些技术必须具有芯片内变化的特性,具有强大的模拟模型,并有特定设计流程的支持,才能在大批量生产中可行。该项目解决了用于大批量集成电路生产的谐振旋转时钟技术的设计和设计自动化方面的挑战。通过改进的纳米级设计表征和设计自动化方法,旋转时钟技术可以无缝地集成到主流VLSI IC设计流程中。拟议研究的更广泛影响是,为低功耗、多GHz操作的数字VLSI同步电路的时钟同步方法带来革命性的变化,并提供其在半导体技术扩展方面的可持续性。拟议的低功率、多GHz高性能时钟操作将对所有微电子系统产生重大影响,从可现场部署的低功率传感器到世界上最快的超级计算机。研究成果将通过一个维基网站和一本书传播。另一个重要的教育影响是将纳米计算和技术概念整合到计算机工程课程中。作为正在进行的费城推广项目的组成部分,计划为高中生举办一个关于计算机的讲习班。
英文摘要
"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant rotary clocking technology for high-volume IC production.With improved nanoscale design characterization and design automation methodologies, rotary clocking technology can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of the proposed research are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers. The research accomplishments will be disseminated through a wiki site and a book. Another important educational impact is on integrating nano-computing and technology concepts into computer engineering curriculum. A workshop on computing is planned for high school students as an integral part of the ongoing outreach projects in urban Philadelphia.
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CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems
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  • 财政年份:
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CSR: Medium: Collaborative Research: Architecture and System Support for Power-Agile Computing
  • 批准号:
    1409014
  • 项目类别:
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  • 资助金额:
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II-NEW: Testbed for High Performance Interconnects
  • 批准号:
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  • 资助金额:
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  • 负责人:
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海外基金