CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems

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Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.