MCDA: Efficient Mechanisms for Multicore Processors

MCDA：多核处理器的高效机制

• 批准号: 0903109
• 负责人: William Dally
• 金额: $ 40.4万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-08-01 至 2013-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0903109&HistoricalAwards=false
• 关键词: MCDA; Efficient; Mechanisms; Multicore; Processors

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."Mainstream computing - on the desktop, in the datacenter, and in embedded devices - is undergoing an unprecedented shift toward parallelism as manufacturers adopt multi-core architectures. Conventional multi-core processors have very inefficient communication, synchronization, and locality-management mechanisms causing them to scale poorly on hard problems and to be difficult to program. The research proposes to develop a set of efficient mechanisms - hardware APIs and supporting microarchitecture - for communication, synchronization, and locality management. Specifically, the project proposes to develop an agile memory hierarchy, register-based communication and synchronization, and fast active messages. By reducing communication and synchronization overhead by orders of magnitude, it is possible to substantially improve the efficiency, programmability, and scalability of multi-core processors. Overall, the mechanisms will free programmers from the incidental constraints imposed by conventional multi-core architectures - allowing them to concentrate instead on the fundamental issues of parallelism, locality, and load balance. The proposed work is expected to have an immense impact on future architecture and programming systems for multi-core processors. By reducing communication and synchronization overheads, the mechanisms will enable many applications that are not embarrassingly parallel to benefit from multi-core architectures. The work is likely to enable a new generation of multi-core programming systems. The educational plan includes to integrate the results of this research into graduate and undergraduate courses at Stanford University.

“这项奖励是根据2009年美国复苏和再投资法案（公法111-5）资助的。”随着制造商采用多核架构，主流计算——在桌面、数据中心和嵌入式设备上——正在经历前所未有的向并行化的转变。传统的多核处理器具有非常低效的通信、同步和位置管理机制，导致它们在处理难题时伸缩性差，而且难以编程。该研究建议开发一套高效的机制——硬件api和支持微架构——用于通信、同步和局部性管理。具体来说，该项目建议开发一个敏捷的内存层次结构，基于寄存器的通信和同步，以及快速的活动消息。通过在数量级上减少通信和同步开销，可以大大提高多核处理器的效率、可编程性和可伸缩性。总的来说，这些机制将把程序员从传统的多核架构带来的附带约束中解放出来——允许他们把精力集中在并行性、局部性和负载平衡等基本问题上。所提出的工作预计将对未来的多核处理器架构和编程系统产生巨大影响。通过减少通信和同步开销，这些机制将使许多并行性不高的应用程序受益于多核体系结构。这项工作很可能使新一代的多核编程系统成为可能。该教育计划包括将这项研究的结果整合到斯坦福大学的研究生和本科课程中。