CSA -- SGER: Efficient, Programmable, Embedded Computing

CSA -- SGER：高效、可编程、嵌入式计算

• 批准号: 0630543
• 负责人: William Dally
• 金额: $ 7.52万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-06-01 至 2007-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0630543&HistoricalAwards=false
• 关键词: CSA; SGER; Efficient; Programmable; Embedded

The bulk of computing today, measured by CPUs, operations, or dollars, is embedded and deals with processing of real-world or ?media? data. Today, most compute-intensive embedded media processing is performed by hard-wired, fixed-function chips (application-specific integrated circuits or ASICs), not by programmable processors. Cell phone modems, WiFi, WiMax, and UWB modems, video codecs, digital television de-interlacers and scalers, for example, are all implemented as hard-wired fixed-function blocks. Designers choose ASICs to implement these functions today for efficiency. The power efficiency (Ops/W) and the area efficiency (Ops/mm2 ) of an ASIC is one to two orders of magnitude more efficient than the most efficient programmable processors available today. However, developing such ASICs is expensive and time consuming. The lack of an efficient, programmable, embedded processor inhibits the development of many embedded applications and slows the evolution of others. This project plans to develop a an efficient, programmable, embedded processor that equals or exceeds the efficiency (Ops/W or Ops/mm2) of a conventional ASIC and is one to two orders of magnitude more efficient than conventional programmable processors. If successful, our research will also reduce the development cost and improve the efficiency of ASICs. To achieve this goal, the project will first identify the major sources of inefficiency in conventional architectures and then systematically develop new microarchitecture techniques to improve efficiency. Particular attention will be given to instruction sequencing and data movement which account for much of the inefficiency of conventional processors. Novel instruction sequencing schemes that capture critical loops in a small number of instruction registers and efficient data storage organizations based on distributed and indexable register files will be investigated. The project will also investigate compilation methods to target these novel architecture elements. The development of an efficient, programmable architecture will open the door to rapid development, evaluation, and deployment of a wide variety of embedded applications with performance levels not previously possible. Research on algorithms for modems, data compression, beamforming, image understanding, and sensor networks, for example will be transformed by the availability of a programmable platform orders of magnitude more efficient than conventional processors. The availablility of this architecture will also make highly-efficient embedded systems available for niche applications (e.g, scientific instrumentation) that could not previously justify the high non-recurring costs of ASICs.

今天的大部分计算，以CPU，操作或美元来衡量，都是嵌入式的，处理现实世界的处理，还是？媒体？数据今天，大多数计算密集型嵌入式媒体处理是由硬连线的固定功能芯片（专用集成电路或ASIC）执行的，而不是由可编程处理器执行的。例如，手机调制解调器、WiFi、WiMax和UWB调制解调器、视频编解码器、数字电视去隔行器和缩放器都被实现为硬连线的固定功能块。今天，设计人员选择ASIC来实现这些功能，以提高效率。ASIC的功率效率（Ops/W）和面积效率（Ops/mm 2）比当今最高效的可编程处理器高出一到两个数量级。然而，开发这样的ASIC是昂贵且耗时的。缺乏高效、可编程的嵌入式处理器抑制了许多嵌入式应用的开发，并减缓了其他应用的发展。该项目计划开发一种高效、可编程的嵌入式处理器，其效率等于或超过传统ASIC的效率（Ops/W或Ops/mm 2），并且比传统可编程处理器的效率高一到两个数量级。如果成功，我们的研究还将降低ASIC的开发成本，提高效率。为了实现这一目标，该项目将首先确定传统架构中效率低下的主要原因，然后系统地开发新的微架构技术来提高效率。将特别注意指令排序和数据移动，占传统处理器的效率低下。新颖的指令排序计划，捕捉关键循环在少量的指令寄存器和有效的数据存储组织的基础上分布式和可索引的寄存器文件将进行调查。该项目还将研究针对这些新颖架构元素的编译方法。开发一个高效的、可编程的体系结构将为快速开发、评估和部署各种各样的嵌入式应用程序打开大门，这些应用程序的性能水平以前是不可能的。调制解调器、数据压缩、波束形成、图像理解和传感器网络等算法的研究将因可编程平台的可用性而发生转变，其效率将比传统处理器高出几个数量级。这种架构的可用性还将使高效的嵌入式系统可用于利基应用（例如，科学仪器），这些应用以前无法证明ASIC的高非经常性成本是合理的。