TC: Medium: Collaborative Research: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection

TC：中：协作研究：具有集成多层保护的侧通道防护嵌入式处理器

• 批准号: 0904943
• 负责人: Jia Di
• 金额: $ 10万
• 依托单位: University of Arkansas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0904943&HistoricalAwards=false
• 关键词: TC; Medium; Collaborative; Research; Side

Abstract: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer ProtectionEmbedded digital systems are ubiquitous and may contain sensitive information that could be used for malicious purposes if fallen into the wrong hands. Therefore, strong cryptographic algorithms have been incorporated inside these devices. However, attackers have switched their targets from the cryptographic algorithms themselves to the hardware/software implementations of these algorithms, through ?side-channel? chip measurements. From a hardware perspective, such side-channel attacks can be implemented at both the circuit-level and architecture-level. Although much research has been performed in mitigating side-channel attacks, these solutions are inflexible, unsystematic, and have high overhead. The goal of this research is to develop a universal solution that synergistically combines both architecture-level and circuit-level countermeasures for mitigating all major categories of side-channel attacks, to yield an extremely secure, highly flexible, low overhead digital system design methodology. In this proof-of-concept project, preliminary research will be carried out at both levels. At the architecture-level, novel architectural support to mitigate architecture-level timing and access-driven attacks will be developed. At the circuit-level, Delay-Insensitive Ternary Logic will be utilized to design the new architectural support as well as other key components of a MIPS32 4K-compatible embedded microprocessor. The effectiveness and efficiency of side-channel attack resistance at both architecture-level and circuit-level will be evaluated. Educational modules of circuit-level and architecture-level attack mitigation will be developed. Graduate and undergraduate students, especially from underrepresented groups, will be involved in this project. The research outcome will be disseminated to the academic and industrial communities through journal articles, conference presentations, and appropriate websites.

摘要：具有集成多层保护的侧通道嵌入式处理器嵌入式数字系统无处不在，并且可能包含敏感信息，如果落入坏人之手，这些信息可能会被用于恶意目的。因此，这些设备中已采用了强大的加密算法。然而，攻击者通过“旁道”将目标从加密算法本身转向这些算法的硬件/软件实现。芯片测量。从硬件角度来看，这种旁路攻击可以在电路级和架构级上实现。尽管在减轻侧信道攻击方面已经进行了大量研究，但这些解决方案不灵活、不系统，并且开销较高。本研究的目标是开发一种通用解决方案，协同结合架构级和电路级对策，以减轻所有主要类别的侧信道攻击，从而产生极其安全、高度灵活、低开销的数字系统设计方法。在这个概念验证项目中，初步研究将在两个层面上进行。在架构级别，将开发新颖的架构支持来减轻架构级别的计时和访问驱动的攻击。在电路层面，延迟不敏感三态逻辑将用于设计新的架构支持以及 MIPS32 4K 兼容嵌入式微处理器的其他关键组件。将评估架构级和电路级侧信道攻击抵抗的有效性和效率。将开发电路级和架构级攻击缓解的教育模块。研究生和本科生，特别是来自代表性不足群体的学生，将参与该项目。研究成果将通过期刊文章、会议演示和适当的网站传播给学术界和工业界。