CSR:Small: A Control-Theoretic Approach to Simultaneously Meeting Timing and Power/Thermal Constraints for Multi-Core Embedded Systems

该奖项是根据2009年美国复苏和再投资法案（公法111-5）资助的。高性能实时嵌入式系统对关键性能属性有严格的要求，例如端到端的及时性和可靠性，以便正常运行。 近年来，随着特征尺寸的不断减小和对计算能力需求的不断提高，当今高性能嵌入式系统面临过热甚至热故障的可能性越来越大。 因此，必须明确控制其功耗和温度，以提高可靠性。 另一方面，由于一些众所周知的技术障碍，多核处理器最近已经成为当前处理器发展的主要趋势。 因此，未来的高性能嵌入式系统将配备多核甚至众核处理器。 因此，需要开发新的控制算法，以同时满足多核嵌入式系统的时序和功耗/热约束。本项目旨在开发一个整体的框架，在反馈控制理论的最新进展的基础上，以满足多核处理器的高性能嵌入式系统的时序和功耗/热约束。 我们的框架可以做出三大贡献。 首先，我们的解决方案可以协调不同的控制策略，以满足这两个约束，保证系统的稳定性。 其次，我们提出了新的功率/热控制（封顶）算法的多核处理器，以实现更高的控制精度和系统性能。 第三，我们提出了新的反馈调度算法，利用多核处理器中的新功能，如共享的L2缓存和每个核心的动态电压频率缩放（DVFS），以提高实时性能。 我们还计划研究异构内核，内存电源管理和系统可控性，以实现更好的电源/热控制和及时性保证。

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).High-performance real-time embedded systems have stringent requirements for key performance properties, such as end-to-end timeliness and reliability, in order to operate properly. In recent years, with the continuously decreasing feature size and increasing demand for computational capabilities, today's high-performance embedded systems face an increasing probability of overheating and even thermal failures. As a result, their power consumption and temperature must be explicitly controlled for improved reliability. On the other hand, multi-core processors have recently become the main trend in the current processor development, due to some well-known technological barriers. Consequently, future high-performance embedded systems can be expected to be equipped with multi-core or even many-core processors. Therefore, new control algorithms need to be developed to simultaneously meet the timing and power/thermal constraints for multi-core embedded systems.This project aims to develop a holistic framework, based on recent advances in feedback control theory, to meet both timing and power/thermal constraints for high-performance embedded systems with multi-core processors. Our framework can make three major contributions. First, our solution can coordinate different control strategies to meet both constraints with guaranteed system stability. Second, we propose novel power/thermal control (capping) algorithms for multi-core processors to achieve improved control accuracy and system performance. Third, we propose new feedback scheduling algorithms to utilize the new features available in multi-core processors, such as shared L2 caches and per-core dynamic voltage frequency scaling (DVFS), for improved real-time performance. We also plan to investigate heterogeneous cores, memory power management, and system controllability for better power/thermal control and timeliness guarantees.