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CSR:Small: A Control-Theoretic Approach to Simultaneously Meeting Timing and Power/Thermal Constraints for Multi-Core Embedded Systems

CSR:Small: A Control-Theoretic Approach to Simultaneously Meeting Timing and Power/Thermal Constraints for Multi-Core Embedded Systems
CSR:Small:同时满足多核嵌入式系统的时序和功耗/热约束的控制理论方法
批准号:
0915959
负责人:
Xiaorui Wang
金额:
$21.95万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-09-01 至 2013-08-31

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中文摘要
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英文摘要
This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).High-performance real-time embedded systems have stringent requirements for key performance properties, such as end-to-end timeliness and reliability, in order to operate properly. In recent years, with the continuously decreasing feature size and increasing demand for computational capabilities, today's high-performance embedded systems face an increasing probability of overheating and even thermal failures. As a result, their power consumption and temperature must be explicitly controlled for improved reliability. On the other hand, multi-core processors have recently become the main trend in the current processor development, due to some well-known technological barriers. Consequently, future high-performance embedded systems can be expected to be equipped with multi-core or even many-core processors. Therefore, new control algorithms need to be developed to simultaneously meet the timing and power/thermal constraints for multi-core embedded systems.This project aims to develop a holistic framework, based on recent advances in feedback control theory, to meet both timing and power/thermal constraints for high-performance embedded systems with multi-core processors. Our framework can make three major contributions. First, our solution can coordinate different control strategies to meet both constraints with guaranteed system stability. Second, we propose novel power/thermal control (capping) algorithms for multi-core processors to achieve improved control accuracy and system performance. Third, we propose new feedback scheduling algorithms to utilize the new features available in multi-core processors, such as shared L2 caches and per-core dynamic voltage frequency scaling (DVFS), for improved real-time performance. We also plan to investigate heterogeneous cores, memory power management, and system controllability for better power/thermal control and timeliness guarantees.
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