SHF: Small: An Adaptive Architecture Fabric for Constructing Resilient Multicore Systems

SHF：小型：用于构建弹性多核系统的自适应架构结构

• 批准号: 0916689
• 负责人: Scott Mahlke
• 金额: $ 45万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2013-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0916689&HistoricalAwards=false
• 关键词: SHF; Small; Adaptive; Architecture; Fabric

As semiconductor technologies scale continues to shrink, building fault-tolerant, defect-free microprocessors becomes increasingly difficult. Tighter design constraints, lower operating voltages, and increasing power densities have lead to circuits that are more susceptible to manufacturing defects, transient faults, and wearout-related failures. It is anticipated that future designs will consist of 100 billion transistors, many of which will be unusable due to manufacturing defects and many will fail over time due to wearout and other errors. Traditional mainframes and mission-critical systems rely on redundancy to overcome such failures. Reliability is essentially viewed as a tax that is levied in the form of additional silicon area devoted to constant double and triple checking of results that end-users must pay to ensure correct operation. As reliability concerns invade the desktop and cellphone environments, large scale redundancy is impractical due to the high cost and energy overheads. This research proposes StageNet, a new style of microprocessor architecture in which reliability is not a tax, but rather built in to the natural operation of the system. StageNet is both introspective to enable continuous monitoring and adaptation to reliability hazards and reconfigurable at a fine-grain level to minimize the lifetime performance impact that individual failures have on the system. StageNet consists of three major components: an adaptive computing substrate that enables dynamic reorganization of individual microprocessors, armored cache designs to provide high defect tolerance with low area overhead for on-chip caches, and a dynamic adaptation system to manage the execution of applications and organization of the hardware over its lifetime. The broader impact of this research is that it creates cost-effective ways of dealing with faulty transistors that will enable the proliferation of embedded computers into more aspects of life, where robustness and reliability are current barriers.

随着半导体技术规模的持续缩小，制造容错、无缺陷的微处理器变得越来越困难。更严格的设计约束、更低的工作电压和不断增加的功率密度导致电路更容易受到制造缺陷、瞬时故障和磨损相关故障的影响。预计未来的设计将由1000亿个晶体管组成，其中许多将由于制造缺陷而无法使用，许多将因磨损和其他错误而随着时间的推移而失效。传统大型机和关键任务系统依靠冗余来克服此类故障。可靠性本质上被视为以额外硅面积的形式征收的税，用于对最终用户必须支付的结果进行持续的双重和三次检查，以确保正确的操作。由于可靠性问题渗透到台式机和手机环境中，由于成本和能源开销较高，大规模冗余是不切实际的。这项研究提出了StageNet，这是一种新型的微处理器体系结构，在这种体系结构中，可靠性不是一种税，而是内置在系统的自然操作中。StageNet既是内省的，可以实现持续的监控和适应可靠性风险，也可以在细粒度级别进行重新配置，以最大限度地减少个别故障对系统的终身性能影响。StageNet由三个主要组件组成：支持单个微处理器动态重组的自适应计算基板；为片上高速缓存提供高缺陷容错和低面积开销的装甲高速缓存设计；以及在其生命周期内管理应用程序的执行和硬件组织的动态适配系统。这项研究的更广泛影响是，它创造了处理有故障的晶体管的经济高效的方法，使嵌入式计算机能够扩散到生活的更多方面，在这些方面，健壮性和可靠性是目前的障碍。