SHF: Small: Scaling the Compute Efficiency of General-Purpose Processors

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The growth of the microprocessor industry has led to progress in diversified computing applications, such as health care, education, security, and communications. However, energy consumption has emerged as a barrier to the continued success of the American semiconductor industry. The inability to scale chip voltages at the historic rate has created a difficult design dilemma referred to as dark silicon: more transistors can fit on a chip, but a growing fraction will not be able to be used due to power dissipation limits. To scale performance in this landscape, fundamental increases in the computational efficiency of processors is required to get much more performance for much less energy. To scale computational efficiency, this work develops an architectural approach referred to as Composite Cores. The proposed architecture brings the notion of heterogeneity from between different cores in a processor to within a core. Each composite core will consist of several energy efficient engines that have been customized to particular execution scenarios found in general-purpose applications. A dynamic management system will perform fine-grain mapping of application segments to the most efficient engine. Hardware mechanisms to ensure delay-free migration of program state provide smooth transitions from engine to engine. By dynamically partitioning an application across a set of customized engines, a large portion of the efficiency gains afforded by hardware accelerators on regular codes can be realized on general-purpose applications. The broader impact of this work is that green computing is recognized as one of the most important challenges in the semiconductor industry and more broadly in Computer Science. Composite cores enable general-purpose processors to reach new levels of energy efficiency while not sacrificing the ability to execute arbitrary code.