Collaborative Research:Hierarchical Testing and Yield Enhancement of High End Integrated RF Systems

合作研究：高端集成射频系统的分层测试和良率提升

• 批准号: 0917738
• 负责人: Sule Ozev
• 金额: $ 0.68万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2009-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0917738&HistoricalAwards=false
• 关键词: Collaborative; Research; Hierarchical; Testing; Yield

Project Abstract0545456Ozev, SuleDuke UniversityCAREER: Hierarchical Process Variability Analysis of Analog Circutis Geared for Test and DiganosisElectronic systems are proliferating into the fabric of the society with an ever increasing speed. Even before one new device technology goes into mass manufacturing, scientists start working on next generation technologies. Unfortunately, the ability to control the processing environment nears its natural limits. One direct result of this diminishing process control capability is the increasing variability in component parameters. The performance of analog electronic circuits is especially susceptible to such process variations. As the control over the process diminishes, testing the manufactured parts effectively and efficiently becomes increasingly more important. The testing process becomes all the more essential to ensure product quality and eventual success of the products in the global marketplace. The conflict resulting from the push towards higher performance while the process variability is increasing indicates a dire need for new approaches for the test automation of analog circuits that will be eventually adopted by the industry. The goal of this project is to develop hierarchical methods for process variability analysis that are geared towards test and diagnosis automation. By determining the variance of each intermediate parameter for the fault-free circuit and for many distinct faults, efficient fault-based test and diagnosis approaches can be developed. During fault injection, only a subset of the system building blocks will change. Through the hierarchical analysis approach, the changes in the circuit will prompt reprocessing of only the information that needs to be updated to ensure efficiency. While digital fault-based test and diagnosis methods have enjoyed widespread acceptance from the industry, there has been a resistance in the analog domain mostly due to the discrepancy between the design goals and the definition of what constitutes a fault. With the help of efficient process variability analysis, this project aims at breaking through this barrier by disassociating the fault injection from the pass/fail criteria. Aligning the pass/fail criteria with the specifications of the circuit will initiate a wider acceptance of automated fault-based test and diagnosis in the analog domain.

项目摘要0545456Ozev，苏莱杜克大学CAREER：面向测试和数字的模拟电路的分层工艺可变性分析电子系统正以越来越快的速度扩散到社会的结构中。甚至在一项新设备技术进入大规模生产之前，科学家们就开始研究下一代技术。不幸的是，控制处理环境的能力接近其自然极限。这种过程控制能力减弱的一个直接结果是部件参数的可变性增加。模拟电子电路的性能特别容易受到这种工艺变化的影响。随着对过程控制的减少，有效和高效地测试制造的零件变得越来越重要。为了确保产品质量和产品在全球市场上的最终成功，测试过程变得更加重要。在工艺可变性增加的同时，对更高性能的推动导致的冲突表明，迫切需要用于模拟电路的测试自动化的新方法，该方法最终将被行业采用。该项目的目标是开发面向测试和诊断自动化的过程可变性分析的分层方法。通过确定无故障电路和许多不同故障的每个中间参数的方差，可以开发出有效的基于故障的测试和诊断方法。在故障注入期间，只会更改系统构建块的子集。通过层次分析方法，电路中的变化将仅提示重新处理需要更新的信息，以确保效率。虽然基于数字故障的测试和诊断方法已被业界广泛接受，但在模拟领域一直存在阻力，这主要是由于设计目标和故障定义之间的差异。借助高效的流程可变性分析，该项目旨在通过将故障注入与通过/失败标准分离来突破这一障碍。使合格/不合格标准与电路规格保持一致，将使基于故障的自动化测试和诊断在模拟领域得到更广泛的接受。