CAREER: A Self-Tuning Cache Architecture for Multi-Core Systems

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Due to the increase in design complexity as a result of the paradigm shift from single-core to multi-core technology, designers require advanced optimization techniques to meet design constraints (e.g. power, energy, performance, area) within an ever shrinking time-to-market. Autonomous self-tuning architectures and methodologies enable a system to dynamically adapt to input stimuli to meet design constraints with little or no designer effort. However, self-tuning systems are exceedingly difficult to design, requiring custom algorithms, flexible reconfigurable architectures, non-intrusive self-evaluation techniques, etc. This research explores and architects novel, lightweight, and efficient reconfigurable architectures, algorithms, and methodologies in the context of a self-tuning cache hierarchy for energy efficient embedded systems. This research will provide fundamental knowledge of how core inter-dependencies both complicate and reveal new optimization opportunities and self-tuning methodologies applicable to other system components (e.g. communication topologies and protocols, voltage scaling, task-to-core mapping, etc.). The outcomes will spawn future research endeavors and enhance academic curricula as well as impact society through more rapidly advancing state-of-the-art technology made possible by reducing design time burdens, enabling application designers to focus more heavily on enhanced functionality rather than system optimization. A research group composed largely of underrepresented minorities and women will undertake the project's endeavors. In addition, the project will include an in-depth evaluation of real-life experiences gathered from successful women engineers to provide tangible motivation, which will be disseminated through scholarly publications, summer research experience programs for high school students, as well as seminars for K-12 students, teachers, and parents.