EAGER: Low-Power VLSI Applications of Neuromorphic Circuit Construction with Nanoelectronic Devices

EAGER：使用纳米电子器件构建神经形态电路的低功耗 VLSI 应用

• 批准号: 0954264
• 负责人: Bertan Bakkaloglu
• 金额: $ 5.45万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0954264&HistoricalAwards=false
• 关键词: EAGER; Low; Power; VLSI; Applications

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).The objective of this research is to utilize nanoscale transistors beyond the CMOS scaling roadmap for low power, high accuracy implementation of neural-inspired (neuromorphic) computing modules. These novel devices include feedback FETs, impact ionization MOSFETs, tunneling devices and ferroelectric transistors. The approach to achieve this technology is to use a complex electrical model of a neural computing cell, and map its behavior to a low hardware complexity circuit using future nanoscale transistor models. Known problems associated with these novel devices such as hysteresis behavior and inherent nonlinearity will be investigated as a beneficial property for fundamental analog neural building blocks, such as perceptron, achieving lower power and higher density.This project will be the first application and investigation of nanoscale devices to self-learning neuromorphic computing platforms, enabling a very low power operation. In this seed project, as an application platform traditional VLSI and signal processing functions will be mapped to neuromorphic computing platforms. These functions include receive channel equalizers and branch prediction logic in RISC computers. Integrated circuit design, characterization and modeling, with a deep understanding of future nanoscale devices for VLSI technology is a critical and growing need for the semiconductor industry. There is a growing need to move beyond traditional logic design for signal processing and computing platforms. The experience of using future nanoscale devices for various neuromorphic circuit blocks will be incorporated to graduate level circuits and device modeling classes, with strong emphasis on training future scientists and engineers with creative problem-solving skills in overcoming limitations of future nanoscale devices.

该奖项是根据2009年《美国复苏和再投资法案》(Public Law 111-5)资助的。这项研究的目标是利用超出CMOS规模路线图的纳米级晶体管，实现低功耗、高精度的神经启发(神经形态)计算模块。这些新颖的器件包括反馈FET、碰撞电离MOSFET、隧道器件和铁电晶体管。实现这项技术的方法是使用神经计算单元的复杂电气模型，并将其行为映射到使用未来纳米级晶体管模型的低硬件复杂性电路。与这些新器件相关的已知问题，如滞后行为和固有非线性，将作为基本模拟神经构建块(如感知器)的有益特性进行研究，以实现更低的功率和更高的密度。该项目将是纳米器件在自学习神经形态计算平台中的首次应用和研究，使非常低的功率运行成为可能。在这个种子项目中，作为一个应用平台，传统的VLSI和信号处理功能将映射到神经形态计算平台。这些功能包括RISC计算机中的接收信道均衡器和分支预测逻辑。集成电路的设计、表征和建模，随着对未来纳米级器件的深入了解，对于VLSI技术是半导体行业的关键和日益增长的需求。信号处理和计算平台越来越需要超越传统的逻辑设计。将未来纳米级器件用于各种神经形态电路模块的经验将被纳入研究生水平的电路和器件建模课程，重点是培养具有创造性问题解决技能的未来科学家和工程师，以克服未来纳米级器件的限制。