SHF: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis

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The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In current practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired performance under all process, voltage, and temperature conditions. Although such an expensive approach is acceptable in today's chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. This proposal aims to develop innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive variability models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design, helping illustrate the diverse opportunities of memory design beyond the 10nm node. This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics.