CAREER: Automation Tools for Post-Silicon Debug of Timing Errors in Integrated Circuits

职业:用于集成电路时序错误的硅后调试的自动化工具

基本信息

  • 批准号:
    1053496
  • 负责人:
  • 金额:
    $ 40.15万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2011
  • 资助国家:
    美国
  • 起止时间:
    2011-01-01 至 2016-12-31
  • 项目状态:
    已结题

项目摘要

Complexity and nano-scale non-idealities of modern electronic systems make it hard to achieve a high degree of validation before fabrication. Post-silicon debug of malfunctions is further complicated due to the limited chip interface with the outside world. The existing debug process is predominantly manual, time-consuming, and involves expensive equipments. Consequently, time-to-market and profit are directly at stake.This proposal proposes a methodology for automation of the post-silicon debug process. It relies on embedding and measuring special design structures to verify the "health" of the system, and on analysis methods using these measurements, to debug the cause of errors. Specifically, the attention is towards those malfunctions that manifest themselves in the form of timing errors, which cause setup and hold time violations in logic, and are the most cumbersome type of error to analyze. The proposed methodology identifies on-chip measurement sites of combinational and sequential logic, and analysis methods which are either real-time and workload-dependent, or static and based on guard-band computation, at both design and post-silicon stages.The education goals are improving teaching, diversity, and preparation of undergraduate and graduate students for the engineering practice and research. The following three tasks are proposed: 1) developing and teaching a case study based on the "One Laptop Per Child" project in an inter-disciplinary freshmen-level course; 2) engaging undergraduate students and developing programming assignments to enhance teaching in the VLSI-CAD area; 3) utilizing various resources to recruit women and minorities, and to train undergraduate and graduate students.
现代电子系统的复杂性和纳米尺度的非理想性使得在制造之前很难实现高度的验证。由于与外界的有限芯片接口,故障的硅后调试进一步复杂化。现有的调试过程主要是手动的,耗时的,并涉及昂贵的设备。因此,上市时间和利润直接受到威胁。该提案提出了一种用于硅后调试过程自动化的方法。它依赖于嵌入和测量特殊的设计结构来验证系统的“健康”,并依赖于使用这些测量的分析方法来调试错误的原因。具体而言,注意力集中在那些以时序错误的形式表现出来的故障上,这些故障会导致逻辑中的设置和保持时间违规,并且是最麻烦的错误类型。所提出的方法确定的组合和时序逻辑的片上测量站点,和分析方法,无论是实时和工作负载相关的,或静态的,基于保护带计算,在设计和后硅stages.The教育目标是提高教学,多样性,本科生和研究生的工程实践和研究的准备。提出了以下三项任务:1)在跨学科新生课程中开发和教授基于“每个孩子一台笔记本电脑”项目的案例研究; 2)吸引本科生并开发编程作业,以加强VLSI-CAD领域的教学; 3)利用各种资源招募妇女和少数民族,并培养本科生和研究生。

项目成果

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Azadeh Davoodi其他文献

Azadeh Davoodi的其他文献

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{{ truncateString('Azadeh Davoodi', 18)}}的其他基金

SHF: Small: Explainable Machine Learning for Better Design of Very Large Scale Integrated Circuits
SHF:小:可解释的机器学习,用于更好地设计超大规模集成电路
  • 批准号:
    2322713
  • 财政年份:
    2023
  • 资助金额:
    $ 40.15万
  • 项目类别:
    Standard Grant
SHF: Small: Synthesis of Complex Deep Neural Networks on Distributed Resource-Constrained Devices
SHF:小型:分布式资源受限设备上复杂深度神经网络的综合
  • 批准号:
    2006394
  • 财政年份:
    2020
  • 资助金额:
    $ 40.15万
  • 项目类别:
    Standard Grant
SaTC: STARSS: Small: Analysis of Security and Countermeasures for Split Manufacturing of Integrated Circuits
SaTC:STARSS:小型:集成电路分片制造的安全性及对策分析
  • 批准号:
    1812600
  • 财政年份:
    2018
  • 资助金额:
    $ 40.15万
  • 项目类别:
    Standard Grant
SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits
SHF:小型:弥合集成电路全局布线和详细布线之间的差距
  • 批准号:
    1608040
  • 财政年份:
    2016
  • 资助金额:
    $ 40.15万
  • 项目类别:
    Standard Grant
SHF:Small:Parallel ILP-Based Global Routing on A Grid of Multi-Cores
SHF:Small:多核网格上基于并行 ILP 的全局路由
  • 批准号:
    0914981
  • 财政年份:
    2009
  • 资助金额:
    $ 40.15万
  • 项目类别:
    Standard Grant
CPA-DA: Robust Performance Characterization in Complex VLSI Design Under Variations
CPA-DA:复杂 VLSI 设计变化下的稳健性能表征
  • 批准号:
    0811082
  • 财政年份:
    2008
  • 资助金额:
    $ 40.15万
  • 项目类别:
    Continuing Grant

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