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SaTC: STARSS: Small: Analysis of Security and Countermeasures for Split Manufacturing of Integrated Circuits

SaTC: STARSS: Small: Analysis of Security and Countermeasures for Split Manufacturing of Integrated Circuits
SaTC:STARSS:小型:集成电路分片制造的安全性及对策分析
批准号:
1812600
负责人:
Azadeh Davoodi
金额:
$31.22万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2018
资助国家:
美国
项目状态:
已结题
起止时间:
2018-08-01 至 2023-07-31

项目摘要

项目成果

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中文摘要
翻译
集成电路制造已经遍布全球,全球90%以上的制造能力由非美国公司控制。这个项目是研究芯片制造的安全性由一个不受信任的代工厂。这种制造技术被称为分裂制造,其基础是与不可信的代工厂部分共享芯片设计信息,以保护芯片的知识产权。有了这种技术,芯片只有一个具有挑战性的部分是在不受信任的代工厂制造的。其余部分则由一家值得信赖的小型铸造厂完成。具体的研究任务包括:(a)利用机器学习技术决定适当的“分割级别”,将芯片设计文件划分为可信和不可信的部分;(b)开发设计辅助工具来混淆芯片布局文件,以使不受信任的代工厂无法进行逆向工程;(c)开发和公开发布软件工具,以从完整晶片的设计文件生成各种分型制造的实例,以促进这方面的研究。除了发布软件工具外,研究成果还将在硬件安全和集成电路设计领域相关的社区发布。该项目的具体组成部分旨在促进本科生参与研究。将在各级推动妇女和代表性不足的学生参与研究。数据和软件工具将从http://homepages.cae.wisc.edu/~adavoodi/split-man.htm公开访问,并将在奖项结束后至少两年内保持活跃。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Integrated circuit fabrication has spread across the globe, with over 90% of the world's fabrication capacity controlled by non-US companies. This project is on studying the security of chip fabrication by an untrusted foundry. The fabrication technique, known as split manufacturing, is based on partial sharing of the chip design information with the untrusted foundry in order to protect the intellectual property of the chip. With this technique, only a challenging portion of the chip is manufactured at the untrusted foundry. The remaining is completed by a trusted and smaller-scale foundry. Specific research tasks include: (a) use of machine learning techniques to decide an appropriate "split level" to divide the chip design files into trusted and untrusted portions; (b) developing design-aid tools to obfuscate the chip layout files in order to make reverse engineering by the untrusted foundry infeasible; (c) development and public release of a software tool to generate various split-manufactured instances from the design files of the full chip, in order to promote research in this area.Besides the release of the software tool, research findings will be published across communities related to the fields of hardware security and Integrated Circuit design. Specific components of the project are designed to promote involvement of undergraduate students in research. Involvement of women and underrepresented students in research will be pursued at all levels.Data and software tools will be publicly accessible from http://homepages.cae.wisc.edu/~adavoodi/split-man.htm and will remain active for at least two years following the end date of the award.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(4)
专著(0)
科研奖励(0)
会议论文
Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns
Lorax:基于机器学习的 Oracle 重构,具有最少的 I/O 模式
DOI: 10.1109/isvlsi51109.2021.00033
发表时间: 2021
期刊: 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI
影响因子: --
作者: [Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit Onur]
通讯作者: Topaloglu, Rasit Onur
ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack
ObfusX:通过机器学习攻击的解释性分析进行路由混淆
DOI: 10.1016/j.vlsi.2022.10.013
发表时间: 2023
期刊: Integration
影响因子: 1.9
作者: [Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit Onur]
通讯作者: Topaloglu, Rasit Onur
Analysis of Security of Split Manufacturing Using Machine Learning
使用机器学习分析分割制造的安全性
DOI: 10.1109/tvlsi.2019.2929710
发表时间: 2019
期刊: IEEE transactions on very large scale integration VLSI systems
影响因子: --
作者: [Zeng, W, Zhang, B, Davoodi, A.]
通讯作者: Davoodi, A.
SHF: Small: Explainable Machine Learning for Better Design of Very Large Scale Integrated Circuits
  • 批准号:
    2322713
  • 项目类别:
    Standard Grant
  • 资助金额:
    $59.98万
  • 财政年份:
    2023
  • 负责人:
    Azadeh Davoodi
  • 依托单位:
SHF: Small: Synthesis of Complex Deep Neural Networks on Distributed Resource-Constrained Devices
  • 批准号:
    2006394
  • 项目类别:
    Standard Grant
  • 资助金额:
    $49.99万
  • 财政年份:
    2020
  • 负责人:
    Azadeh Davoodi
  • 依托单位:
SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits
  • 批准号:
    1608040
  • 项目类别:
    Standard Grant
  • 资助金额:
    $40.0万
  • 财政年份:
    2016
  • 负责人:
    Azadeh Davoodi
  • 依托单位:
CAREER: Automation Tools for Post-Silicon Debug of Timing Errors in Integrated Circuits
  • 批准号:
    1053496
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $40.15万
  • 财政年份:
    2011
  • 负责人:
    Azadeh Davoodi
  • 依托单位:
海外基金