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SaTC: STARSS: Small: Analysis of Security and Countermeasures for Split Manufacturing of Integrated Circuits

SaTC：STARSS：小型：集成电路分片制造的安全性及对策分析

基本信息

批准号：
1812600
负责人：
Azadeh Davoodi
金额：
$ 31.22万
依托单位：
University of Wisconsin-Madison
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2018
资助国家：
美国
起止时间：
2018-08-01 至 2023-07-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1812600&HistoricalAwards=false
关键词：
SaTC STARSS Small Analysis Security

项目摘要

Integrated circuit fabrication has spread across the globe, with over 90% of the world's fabrication capacity controlled by non-US companies. This project is on studying the security of chip fabrication by an untrusted foundry. The fabrication technique, known as split manufacturing, is based on partial sharing of the chip design information with the untrusted foundry in order to protect the intellectual property of the chip. With this technique, only a challenging portion of the chip is manufactured at the untrusted foundry. The remaining is completed by a trusted and smaller-scale foundry. Specific research tasks include: (a) use of machine learning techniques to decide an appropriate "split level" to divide the chip design files into trusted and untrusted portions; (b) developing design-aid tools to obfuscate the chip layout files in order to make reverse engineering by the untrusted foundry infeasible; (c) development and public release of a software tool to generate various split-manufactured instances from the design files of the full chip, in order to promote research in this area.Besides the release of the software tool, research findings will be published across communities related to the fields of hardware security and Integrated Circuit design. Specific components of the project are designed to promote involvement of undergraduate students in research. Involvement of women and underrepresented students in research will be pursued at all levels.Data and software tools will be publicly accessible from http://homepages.cae.wisc.edu/~adavoodi/split-man.htm and will remain active for at least two years following the end date of the award.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

集成电路制造已遍布地球仪，全球90%以上的制造能力由非美国公司控制。本计画是关于不可信代工厂生产晶片的安全性研究。制造技术，被称为分裂制造，是基于与不可信的代工厂部分共享芯片设计信息，以保护芯片的知识产权。通过这种技术，只有芯片的一个具有挑战性的部分在不受信任的代工厂生产。其余的由一个值得信赖的小规模铸造厂完成。具体研究任务包括：（a）使用机器学习技术来决定将芯片设计文件划分为可信和不可信部分的适当“划分级别”;（B）开发设计辅助工具来混淆芯片布局文件，以便使不可信代工厂的逆向工程不可行;（c）开发和公开发布一个软件工具，以便从整个芯片的设计文件生成各种分开制造的实例，以促进这方面的研究。除了发布软件工具外，研究成果将在与硬件安全和集成电路设计领域相关的社区中发布。该项目的具体组成部分旨在促进本科生参与研究。妇女和代表性不足的学生参与研究将在各级进行。数据和软件工具将在http://homepages.cae.wisc.edu/~adavoodi/split-man.htm上公开访问，并将在奖项结束后至少两年内保持活跃。该奖项反映了NSF的法定使命，并被认为值得通过使用基金会的知识价值和更广泛的影响审查标准进行评估来支持。