SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits

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As semiconductor technology enters the sub-10nm era, it has significantly complicated the computer-aided design (CAD) of integrated circuits (ICs). Today's designer must deal with increasingly complex rules, imposed by the manufacturing facility so as to ensure that the chip can be successfully fabricated. This project aims to develop CAD tools that incorporate major design rules within a key, higher stage of the design flow, namely the global routing stage. By integrating these rules into global routing, the project aims to accelerate the progress of IC design within the sub-10nm regime. Other broader goals of the project include: public release of a version of the tools developed to facilitate academic research, technology transfer to major semiconductor companies, integration with two existing courses at UW-Madison, and training graduate and undergraduate students to gain the necessary skills for today's IC-CAD job market.The project tasks are centered around investigating design-rule-aware models at the global routing level of abstraction, including machine-learning techniques for better pin-access planning. In addition, the project will identify new routing challenges caused by modern design rules and will investigate appropriate optimization strategies, including graph-based and mathematical programming techniques, to address them.