SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits

随着半导体技术进入亚10纳米时代，它使集成电路（IC）的计算机辅助设计（CAD）变得非常复杂。今天的设计师必须处理越来越复杂的规则，由制造设施强加，以确保芯片可以成功制造。该项目旨在开发CAD工具，将主要设计规则纳入设计流程的一个关键的更高阶段，即全球布线阶段。通过将这些规则集成到全局布线中，该项目旨在加速10纳米以下IC设计的进展。该项目的其他更广泛目标包括：公开发布开发的工具版本，以促进学术研究，技术转移到主要的半导体公司，与威斯康星大学麦迪逊分校现有的两门课程的整合，并培训研究生和本科生，以获得必要的技能，为今天的IC-CAD就业市场。该项目的任务是围绕调查设计规则，全局布线抽象级别的感知模型，包括用于更好的引脚访问规划的机器学习技术。此外，该项目还将确定现代设计规则带来的新的布线挑战，并将研究适当的优化策略，包括基于图形和数学编程技术，以解决这些问题。

As semiconductor technology enters the sub-10nm era, it has significantly complicated the computer-aided design (CAD) of integrated circuits (ICs). Today's designer must deal with increasingly complex rules, imposed by the manufacturing facility so as to ensure that the chip can be successfully fabricated. This project aims to develop CAD tools that incorporate major design rules within a key, higher stage of the design flow, namely the global routing stage. By integrating these rules into global routing, the project aims to accelerate the progress of IC design within the sub-10nm regime. Other broader goals of the project include: public release of a version of the tools developed to facilitate academic research, technology transfer to major semiconductor companies, integration with two existing courses at UW-Madison, and training graduate and undergraduate students to gain the necessary skills for today's IC-CAD job market.The project tasks are centered around investigating design-rule-aware models at the global routing level of abstraction, including machine-learning techniques for better pin-access planning. In addition, the project will identify new routing challenges caused by modern design rules and will investigate appropriate optimization strategies, including graph-based and mathematical programming techniques, to address them.