SHF: Small: Collaborative Research: A Novel Method for the Performance Analysis of VLSI Circuits with Severe Parameter Value Variations due to Nano-scale Process

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The advance of VLSI technology has reached to 32nm feature size and below. For such a nano-scale process, lithography no longer produces the ideal shape/dimension of circuit components in a silicon wafer, and the corresponding electrical parameters may vary as large as 1/3 or more. A major concern in VLSI design is how to evaluate the circuits/systems performance made in such nano-scale process. In the other words, we want to know how much the performance specs will change due to variation in circuit parameters from their nominal values caused by the process uncertainties. The current research on performance robustness analysis is developed mainly along the line of the Monte-Carlo sampling method, or stochastic and statistical analysis methods. They all require a high level of computation complexity to achieve the required accuracy and one would like to avoid the evaluation of large number of samples to validate the performance range of a VLSI circuit/system? In this research the PIs propose a novel method for VLSI circuit performance robustness analysis which does not require evaluation of large numbers of samples. Instead, it computes only a few critical polynomials in frequency domain, or critical systems in time domain. It is a fundamentally new way to analyze VLSI circuit performance robustness. The consequent leap of computation efficiency would make nano-scale VLSI circuit design and its performance robustness analysis practically possible. The objectives of this project are: (i) to develop a solid theoretical basis for the performance robustness analysis of VLSI circuits in both frequency and time domains; (ii) to develop an efficient, novel method for computing VLSI circuit performance variation bounds and distribution (due to the process variation) without using the Monte-Carlo method.The broad impact of this project will be its potentially transformative effect on the robust analysis methods for VLSI circuits. This research will be integrated into the graduate education of the Ph.D. students at the two universities involved, and disseminated by publications in journals and presentations at conferences, a workshop and collaboration with industry, and will hopefully contribute to broad thinking across multiple disciplines.