SHF: Small: Collaborative Research: A Novel Method for the Performance Analysis of VLSI Circuits with Severe Parameter Value Variations due to Nano-scale Process

SHF：小型：协作研究：一种用于纳米级工艺导致参数值变化严重的 VLSI 电路性能分析的新方法

• 批准号: 1115564
• 负责人: Sheng-Guo Wang
• 金额: $ 22.5万
• 依托单位: University of North Carolina at Charlotte
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1115564&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Novel

The advance of VLSI technology has reached to 32nm feature size and below. For such a nano-scale process, lithography no longer produces the ideal shape/dimension of circuit components in a silicon wafer, and the corresponding electrical parameters may vary as large as 1/3 or more. A major concern in VLSI design is how to evaluate the circuits/systems performance made in such nano-scale process. In the other words, we want to know how much the performance specs will change due to variation in circuit parameters from their nominal values caused by the process uncertainties. The current research on performance robustness analysis is developed mainly along the line of the Monte-Carlo sampling method, or stochastic and statistical analysis methods. They all require a high level of computation complexity to achieve the required accuracy and one would like to avoid the evaluation of large number of samples to validate the performance range of a VLSI circuit/system? In this research the PIs propose a novel method for VLSI circuit performance robustness analysis which does not require evaluation of large numbers of samples. Instead, it computes only a few critical polynomials in frequency domain, or critical systems in time domain. It is a fundamentally new way to analyze VLSI circuit performance robustness. The consequent leap of computation efficiency would make nano-scale VLSI circuit design and its performance robustness analysis practically possible. The objectives of this project are: (i) to develop a solid theoretical basis for the performance robustness analysis of VLSI circuits in both frequency and time domains; (ii) to develop an efficient, novel method for computing VLSI circuit performance variation bounds and distribution (due to the process variation) without using the Monte-Carlo method.The broad impact of this project will be its potentially transformative effect on the robust analysis methods for VLSI circuits. This research will be integrated into the graduate education of the Ph.D. students at the two universities involved, and disseminated by publications in journals and presentations at conferences, a workshop and collaboration with industry, and will hopefully contribute to broad thinking across multiple disciplines.

VLSI技术的进步已经达到了32 nm及以下的特征尺寸。对于这样的纳米级工艺，光刻不再产生硅片中电路元件的理想形状/尺寸，相应的电气参数可能变化高达三分之一或更多。在VLSI设计中，一个重要的问题是如何评估在这种纳米级工艺下制造的电路/系统的性能。换句话说，我们想知道由于工艺不确定性引起的电路参数与其标称值的变化，性能规格将发生多大变化。目前性能稳健性分析的研究主要沿着蒙特卡罗抽样方法或随机统计分析方法的方向发展。它们都需要很高的计算复杂性才能达到所需的精度，而且人们希望避免评估大量样本来验证VLSI电路/系统的性能范围？在这项研究中，PI提出了一种新的VLSI电路性能稳健性分析方法，该方法不需要评估大量的样本。相反，它只在频域中计算几个临界多项式，或者在时间域中计算临界系统。这是一种全新的分析VLSI电路性能稳健性的方法。随之而来的计算效率的飞跃将使纳米级VLSI电路设计及其性能稳健性分析成为可能。该项目的目标是：(I)为VLSI电路的性能稳健性分析在频域和时域上提供坚实的理论基础；(Ii)开发一种高效、新颖的方法来计算VLSI电路的性能变化界和分布(由于工艺变化)，该项目的广泛影响将是它对VLSI电路健壮性分析方法的潜在变革。这项研究将被整合到两所大学博士生的研究生教育中，并通过期刊上的出版物和在会议、研讨会上的演讲和与业界的合作来传播，并有望有助于跨多个学科的广泛思考。