SHF: Small: Footprint Models and Techniques for Multi-core Cache Management

这项研究旨在开发新的理论和技术，以更好地理解和管理多核体系结构中的共享内存缓存。其核心概念是程序占用，即一段时间内的内存访问量。完整的测量需要在所有执行窗口中计算数据访问，这太昂贵了。这项研究开发了计算方法，首先通过一组新的分析算法使全窗口分析可行，然后通过统计推理、采样和并行分析降低成本，并在程序执行时有效地实时获取这些信息，从而使这种分析具有成本效益。在分析程序和程序任务之间的缓存共享时，足迹信息是必不可少的。它支持项目的第二部分，即一组工具，用于预测并行工作负载的性能，而无需进行并行测试。此外，足迹信息使得对常见技术采取完全不同的方法成为可能。在第三部分中，项目开发了一个新的缓存提示插入工具，以接近最优的缓存和内存性能调整工具，供软件开发人员使用。随着多核处理器的普及和云计算的普及，更多的应用程序在共享环境中运行。本研究的结果将从根本上改变程序员理解和提高多核系统上内存性能的方式。软件开发人员和硬件工程师将有一个新的工具集来解决复杂的芯片内存管理问题，不仅是针对顺序代码，也是针对并行代码，不仅是为了实现良好的性能，而且还为了确保在动态环境中的稳定性能。这项研究的更广泛影响将包括更深入地理解和更精确地描述计算过程中的局部性，这将影响到其他计算相关学科，以及节省能源和成本并具有广泛的经济效益和社会效益的内存节约型软件和硬件设计。

This research aims at developing new theories and techniques tobetter understand and manage shared memory cache in multi-core architectures. The core concept is program footprint, which is the amount of memory access in a period ofexecution. Complete measurement requires counting data access in allexecution windows, which is too costly. Thisresearch develops computational methods to first make all-windowanalysis feasible through a set of new profiling algorithms and thenmake this analysis cost-effective by reducing the cost through statisticalinference, sampling, and parallel profiling and effectively obtainingthis information in real time as a program executes. Footprintinformation is essential in analyzing cache sharing between programsand program tasks. It enables the second part of the project, a setof tools that predict the performance of parallel workloads withoutparallel testing. In addition, the footprint information enables afundamentally different approach to common techniques. In the thirdpart, the project develops a new cache-hint insertion tool toapproximate optimal caching and amemory-performance tuning tool to be used by software developer.As multi-core processors become commonplace and cloud computing isgaining acceptance, more applications are run in a shared environment.The outcome of this research will fundamentally alter the wayprogrammers understand and improve memory performance on multi-coresystems. Software developers and hardware engineers will have a newtool set to tackle the complex problem of managing on-chip memory fornot just sequential but also parallel code and for not just achievinggood performance but also for ensuring stable performance in a dynamicenvironment. The broader impacts of this research will includedeeper understanding and more precise characterization of localityin computational processes, which has implications in othercomputing-related disciplines, and memory efficient software andhardware design, which saves energy and cost and has broad economicaland social benefits.