Collaborative Research: SHF: Small: Programmable Hierarchical Caches: Design, Programming, and Prototyping

随着计算技术变得越来越强大，存储器更大但更复杂，不同的材料、配置和互连在容量、速度和成本之间具有不同的权衡。由于这种复杂性，全自动解决方案越来越不理想和脆弱。 该项目开发了可编程的存储器层次结构的新设计，因此可以实现更好的性能，并提供比当前计算机系统（从智能手机到超级计算机）上使用的传统解决方案更强的保证。 新的可编程性使软件和硬件的优化协调一致。 由于计算机成本和速度取决于存储器层次结构，可编程设计可以克服当前在可扩展性和功率效率方面的限制。除了技术内容外，本项目还推进了计算机存储科学的教学，并努力增加该领域研究和开发参与者的多样性。具体而言，本项目开发了一种称为租赁高速缓存的两级可编程高速缓存系统，并设计了其编程技术。 它有三个部分：租用高速缓存的自动编程和优化;在FPGA板上具有两级租用高速缓存的RISC-V处理器的硬件设计和原型;租用高速缓存理论，特别是该高速缓存性能的统计特性和保证。 通过理论和原型设计，新设计可以保持软件的可移植性，确保在默认情况下与当前自动解决方案的性能相匹配，并提供精确定义的缓存性能属性。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

As computing technology becomes ever more powerful, memory is larger but more complex, with different materials, configurations, and interconnects having different trade-offs among capacity, speed, and cost. Because of this complexity, fully automatic solutions are increasingly sub-optimal and brittle. This project develops new designs of the memory hierarchy that are programmable and therefore can achieve better performance and provide stronger guarantees than conventional solutions used on current computer systems ranging from smartphones to supercomputers. The new programmability enables optimization in software and hardware in concert. Since computer cost and speed depend on memory hierarchy, programmable designs can overcome the current limit in scalability and power efficiency. Beyond its technical content, the project advances teaching in the science of computer memory and strives to increase the diversity among participants in this area of research and development.Specifically, the project develops a two-level programmable cache system called the lease cache and designs its programming techniques. It has three parts: automatic programming and optimization of the lease cache; hardware design and prototyping of a RISC-V processor with the two-level lease cache on an FPGA board; and lease-cache theory especially statistical properties and guarantees of the cache performance. Through theories and prototyping, the new designs can retain software portability, ensure matching performance to current automatic solutions by default, and provide precisely defined cache performance properties.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.