SHF: Small: Methods for Diagnosis of Non-Classical Faults in Digital Circuits

SHF：小型：数字电路中非经典故障的诊断方法

• 批准号: 1116213
• 负责人: Vishwani Agrawal
• 金额: $ 30万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-08-01 至 2014-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116213&HistoricalAwards=false
• 关键词: SHF; Small; Methods; Diagnosis; Non

The research in this project focuses on diagnostic test generation methods for non-classical faults, such as transition delay and bridging faults, which represent the fault behaviors of modern VLSI devices. Although, the existing tools for VLSI circuit testing incorporate years of research they only deal with classical stuck-at faults. A stuck-at fault is detectable by a single input pattern. Detection of a transition fault is more complex because it requires a sequence of two patterns. Also, the existing tools find tests that detect faults and may not diagnose them, i.e., identify the exact cause of a failure. The traditional metric used in testing is fault coverage. This research investigates the use of a new metric termed diagnostic coverage for the effectiveness of tests in their role of fault diagnosis. For example, to distinguish between two faults one must use a test that detects one fault but not the other; such a test is called an exclusive test. This research provides new algorithms to generate tests for diagnosis of non-classical faults while allowing the use of the available testing tools.Moore's law prediction of the number of devices on a VLSI chip doubling every eighteen months simply follows the trend of minimum cost per transistor. The enabling technology driver is the shrinking geometry of features allowing higher transistor density and speed. Nanometer geometries have, however, led to greater process variations. Two characteristics separate the testing of modern VLSI technologies. First, the complex fault mechanisms are no longer represented by the classical stuck-at faults. Second, the impact of increased process variation on yield requires testing to be diagnostic-oriented; faults must be identified so that their causes can be eliminated. The research in this project addresses both needs of the advancing VLSI technology.

本项目的研究重点是针对代表现代VLSI器件故障行为的非经典故障（如过渡延迟和桥接故障）的诊断测试生成方法。尽管现有的VLSI电路测试工具结合了多年的研究，但它们只处理经典的固定故障。固定型故障可通过单个输入模式检测。转换故障的检测更加复杂，因为它需要两个模式的序列。此外，现有的工具发现检测故障的测试，并且可能不诊断它们，即，确定故障的确切原因。测试中使用的传统度量是故障覆盖率。本研究探讨使用一个新的度量称为诊断覆盖率的有效性测试在其故障诊断的作用。例如，为了区分两个故障，必须使用检测到一个故障而不是另一个故障的测试;这种测试称为排他性测试。这项研究提供了新的算法来生成测试诊断的非经典故障，同时允许使用现有的测试tools.摩尔定律预测的器件数量的VLSI芯片上增加一倍，每18个月简单地遵循的趋势，每个晶体管的最低成本。使能技术驱动力是缩小的几何特征，允许更高的晶体管密度和速度。然而，纳米几何形状导致了更大的工艺变化。现代VLSI技术的测试有两个特点。首先，复杂的故障机制不再是典型的固定故障。其次，增加的工艺变化对产量的影响要求测试以诊断为导向;必须识别故障，以便消除其原因。本计画的研究内容，是因应超大规模积体电路技术的发展，同时满足两方面的需求。