SHF: Small: Methods for Diagnosis of Non-Classical Faults in Digital Circuits

本项目的研究重点是非经典故障的诊断测试生成方法，如过渡延迟和桥接故障，它们代表了现代VLSI器件的故障行为。尽管现有的VLSI电路测试工具结合了多年的研究，但它们只处理经典的固定故障。固定故障可以通过一个输入模式检测到。过渡故障的检测更为复杂，因为它需要两种模式的序列。此外，现有工具会找到检测到故障的测试，但可能无法对其进行诊断，即确定故障的确切原因。测试中使用的传统度量是故障覆盖率。这项研究调查了一种名为诊断覆盖率的新指标的使用，以了解测试在故障诊断中的作用。例如，要区分两个故障，必须使用只检测一个故障而不检测另一个故障的测试；这种测试称为排他性测试。这项研究提供了新的算法来生成用于诊断非经典故障的测试，同时允许使用现有的测试工具。摩尔定律预测每18个月VLSI芯片上的器件数量每18个月翻一番，只是遵循每晶体管成本最低的趋势。使技术成为可能的驱动因素是允许更高的晶体管密度和速度的特征的缩小几何形状。然而，纳米几何结构导致了更大的工艺差异。现代VLSI技术的测试有两个特点。首先，复杂的故障机制不再由经典的顽固故障来代表。其次，工艺变化增加对合格率的影响要求测试以诊断为导向；必须识别故障，以便消除其原因。本项目的研究既满足了先进的VLSI技术的需求，也满足了VLSI技术的发展。

The research in this project focuses on diagnostic test generation methods for non-classical faults, such as transition delay and bridging faults, which represent the fault behaviors of modern VLSI devices. Although, the existing tools for VLSI circuit testing incorporate years of research they only deal with classical stuck-at faults. A stuck-at fault is detectable by a single input pattern. Detection of a transition fault is more complex because it requires a sequence of two patterns. Also, the existing tools find tests that detect faults and may not diagnose them, i.e., identify the exact cause of a failure. The traditional metric used in testing is fault coverage. This research investigates the use of a new metric termed diagnostic coverage for the effectiveness of tests in their role of fault diagnosis. For example, to distinguish between two faults one must use a test that detects one fault but not the other; such a test is called an exclusive test. This research provides new algorithms to generate tests for diagnosis of non-classical faults while allowing the use of the available testing tools.Moore's law prediction of the number of devices on a VLSI chip doubling every eighteen months simply follows the trend of minimum cost per transistor. The enabling technology driver is the shrinking geometry of features allowing higher transistor density and speed. Nanometer geometries have, however, led to greater process variations. Two characteristics separate the testing of modern VLSI technologies. First, the complex fault mechanisms are no longer represented by the classical stuck-at faults. Second, the impact of increased process variation on yield requires testing to be diagnostic-oriented; faults must be identified so that their causes can be eliminated. The research in this project addresses both needs of the advancing VLSI technology.