SBIR Phase II: Massively Dense 3D Integrated Memory

这个小型企业创新研究(SBIR)第二阶段项目将使用集成电路(IC)制造中常见的材料，进一步开发一种两端、电子可编程、非易失性存储器阵列。每个元件都比单个晶体管小，并使用标准IC层形成。这导致了使用单个基板实现的三维(3D)集成存储器(3DIM)架构，而不需要将多个芯片或晶片与先进的键合技术组装在一起。这些器件的通断电导比和开关速度超过了竞争技术的性能。电流流经器件的纳米尺寸区域，因此，存储元件将缩放到较小的尺寸，而不会减少流经器件的电流，从而导致密集的存储器阵列体系结构，其具有针对每一后续IC技术的改进的信噪比。提出的总体方案将包括集成钝化层，将每个元件与隔离二极管连接，优化器件架构以最大限度地减少占地面积，以及实现3DIM控制和驱动接口电子产品。这里提出的计划通过提供材料创新来提高电子设备的性能，其中纳米级半导体细丝在用于商业数据存储应用的介质材料中制造。该项目的更广泛的影响/商业潜力是在用于无线、移动互联网和其他使用非易失性存储器的便携式设备的微电子芯片制造领域。记忆器件阵列影响了包括闪存和嵌入式存储器在内的众多商业市场，并提供了比传统存储器高出数量级的密度。通过在单个衬底上实现大规模密集3D存储器阵列架构，不需要制造多个衬底并将它们结合在一起，从而简化了制造工艺，降低了制造成本并提高了成品率。除了便携式设备外，该设备还可能在基于空间的地球科学和天文学中找到应用，因为它对X射线和重离子辐射具有耐受性。最近在单个衬底上实现3D存储的一些方法并不成功，这是因为外场导致比特错误和低信噪比的问题，或者是因为设备操作基于热、离子传输或相变机制，这些机制固有地很慢。拟议的存储元件使用电信号而不是热能或化学能来控制，使它们比竞争对手的技术更高效、更快。存储器阵列将在商业铸造厂制造，并在整个第二阶段项目中按比例缩小到更小的尺寸。

This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.