SBIR Phase II: Massively Dense 3D Integrated Memory

这个小型企业创新研究（SBIR）二期项目将进一步开发一种双端、电子可编程、非易失性存储器阵列，该阵列使用集成电路（IC）制造中常见的材料。每个元件都比单个晶体管小，并使用标准IC层形成。这导致了三维（3D）集成存储器（3DIM）架构的实现，使用单一衬底，而无需将多个芯片或晶圆组装在一起，并采用先进的键合技术。这些器件的ON/OFF电导比和开关速度超过了竞争技术的性能。电流流过器件的纳米尺寸区域，因此，存储元件将缩小尺寸，而不会减少通过器件的电流，从而产生密集的存储阵列架构，并为每个后续IC技术提高信噪比。拟议的整体方案将包括集成一个钝化层，用隔离二极管连接每个元件，优化器件架构以最小化占用空间，并实现3DIM控制和驱动接口电子器件。本文提出的方案通过提供材料创新来改善电子产品的性能，其中纳米级半导体细丝是在商业数据存储应用的介电材料中制造的。该项目的更广泛的影响/商业潜力是在无线、移动互联网和其他使用非易失性存储器的便携式设备的微电子芯片制造领域。记忆器件阵列影响了包括闪存和嵌入式存储器在内的许多商业市场，与传统存储器相比，它提供了更高的密度。通过在单一衬底上实现大规模密集的3D存储阵列架构，无需制造多个衬底并将它们粘合在一起，从而简化了制造工艺，降低了制造成本，提高了成品率。除了便携式设备外，拟议的设备还可用于天基地球科学和天文学，因为它能耐受x射线和重离子辐射。由于外场导致误码和低信噪比的问题，或者由于器件运行基于热、离子传输或相变机制，这些机制本身就很慢，一些最近在单一衬底上实现3D存储器的方法并没有成功。拟议中的存储元件是使用电信号而不是热能或化学能来控制的，这使得它们比竞争对手的技术更高效、更快。存储阵列将在商业铸造厂制造，并在整个二期项目中缩小尺寸。

This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.