SBIR Phase I: Massively Dense 3D Integrated Memory

这个小型企业创新研究第一阶段项目将进一步开发一个双端，电子可编程，非易失性存储器阵列使用集成电路（IC）制造中常见的材料。每个元件都小于单个晶体管，并且使用标准IC层形成。这导致使用单个衬底实现的三维集成存储器（3DIM）架构，而不需要利用先进的键合技术将多个管芯附接在一起。这些器件的导通/截止电导比和开关速度超过了竞争技术的性能。电流流过器件的纳米尺寸区域，并且因此，随着IC技术继续朝着更小的特征尺寸发展，每个器件将缩放到更小的尺寸，而不减少通过器件的电流，从而导致具有信噪比的密集存储器阵列架构，该信噪比将针对每个后续IC技术而改善。拟议的整体计划将包括集成钝化层，将每个元件与二极管连接，优化器件架构以最大限度地减少占地面积，以及实施3DIM控制和驱动接口电子器件。本文提出的计划通过提供材料创新来提高电子产品的性能，其中纳米级半导体细丝在电介质材料中制造，用于商业数据存储应用，该项目的更广泛影响/商业潜力是在无线，手持，移动的互联网和其他使用非易失性存储器的便携式设备的微电子芯片制造领域。展现出双端、电子可编程电导的材料可能会影响包括闪存和嵌入式存储器在内的众多商业市场，并将提供比当前可用的存储器技术高几个数量级的数据存储密度。通过在单个衬底上实现大规模密集3D存储器阵列架构，不需要制造两个衬底并将它们结合在一起，从而大大简化了制造工艺，降低了制造成本并提高了产品良率。在单个衬底上实现3D存储器的一些最近的方法尚未成功，这是由于外部场导致位错误和低信噪比的问题，或者因为器件操作基于固有地慢的热、离子传输或相变机制。所提出的存储元件是使用电信号而不是热能或化学能来控制的，这使得它们比竞争技术更高效、更快。除了便携式设备之外，所提出的3D设备还可以在天基地球科学和天文学中找到应用，因为它可以耐受X射线和高能质子辐射。计划对其他辐射类型进行额外测试。

This Small Business Innovation Research Phase I project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional integrated memory (3DIM) architecture achieved using a single substrate without the need for attaching multiple die together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, each device will scale to smaller dimensions as IC technology continues to progress towards smaller feature sizes without reducing the current through the device, thereby resulting in a dense memory array architecture with signal-to-noise ratio that will improve for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with a diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, hand-held, mobile internet and other portable devices using non-volatile memory. Materials exhibiting two-terminal, electronically-programmable conductance can potentially impact numerous commercial markets including flash and embedded memory, and will offer orders of magnitude more data storage density as currently-available memory technologies. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate two substrates and bond them together, thereby greatly simplifying the fabrication process, reducing manufacturing cost and increasing product yield. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and much faster than competing technologies. In addition to portable devices, the proposed 3D device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and high-energy proton radiation. Additional testing in planned for other radiation types.