Probabilistic-based Ultra-Low Supply Voltage Noise-Tolerant Circuits and Systems Design

功耗已经成为集成电路设计的关键性能指标，特别是在基于电池的便携式系统中。降低电源电压是降低能耗的最有效和最普遍的技术之一，因为功率与电源电压的平方成正比。然而，当CMOS器件按摩尔定律缩小时，噪声容忍度成为纳米级电路生存的瓶颈。此外，低电压cmos系统中较小的噪声容限使其对噪声更加敏感。软故障(由固有噪声和信号耦合引起)和硬故障(由制造工艺的可变性和缺陷引起)是纳米级电路中的一个明显问题。然而，随机和动态噪声并没有随着电源电压的减小而成比例地降低，这成为低电源电压设计的主要挑战。 这笔发现补助金将用于支持申请者正在进行的马尔可夫随机场(MRF)研究。我们的长期目标是开发一种改变游戏规则的基于概率的方法，这种方法可以影响未来的CMOS设计。磁流变技术广泛应用于信号处理和通信系统中。它对硬件电路的创造性扩展(由申请人首创)既具有很高的创新性，又在解决纳米级电路中的固有软故障和硬故障方面具有巨大回报。自2003年在IEEE/ACM国际计算机辅助设计会议上首次发表以来，他与人合著的关于磁流变电路设计的里程碑式论文被引用115次。该研究小组还实现了世界上第一个使用0.13-m CMOS工艺技术进行验证的概念验证MRF加法器。结果表明，该电路能在超低电源电压下可靠工作，实现了显著的节电效果。他们在第七届MXIC设计大赛(台湾规模最大、最具影响力的年度IC设计大赛)上获得最佳创新奖。自2003年以来，世界各地的许多研究小组都遵循并改进了MRF设计方法。 这笔发现基金将在未来5年提供运营资金，支持申请者继续探索MRF设计的潜力：特别是优化概率设计方法，并应用MRF设计方法来实施大规模信号处理和通信系统。探索助学金的三分之二将用于培训学生。申请者将利用这笔赠款中的研究发现，促进从合作行业和政府项目中获得其他资金。申请者预计这笔赠款将对加拿大低功率电子行业产生重大影响，在信息和通信技术领域以及便携式电池供电的医疗设备领域有着广泛的应用。

Power consumption has become a key performance criterion for integrated circuit design, especially in battery-based portable systems. Decreasing supply voltage is one of the most efficient and universal techniques to reduce energy dissipation because power is proportional to the square of supply voltage. However, when CMOS devices are scaled down following Moore's law, noise tolerance becomes the bottleneck for the viability of nanoscale circuits. Furthermore, the smaller noise margin in low-voltage CMOS systems renders them even more sensitive to noise. Soft faults (caused by inherent noise and signal coupling) and hard faults (caused by variability and defects of fabrication technologies) present an obvious problem in nanoscale circuits. Random and dynamic noise, however, do not decrease in the same proportion as supply voltage is scaled down, which becomes a major challenge for low-supply-voltage designs. This Discovery Grant will be used to support the applicant's ongoing Markov Random Field (MRF) research. The long-term goal is to develop a game-changing probabilistic-based methodology, which can influence future CMOS design. MRF technology is commonly used in signal processing and communication systems. Its creative extension to hardware circuits (pioneered by the applicant) is both highly innovative and with the potential for great rewards in solving intrinsic soft faults and hard faults in nanoscale circuits. His co-authored milestone paper on MRF circuit design was cited 115 times since it was first published in IEEE/ACM international conference on computer-aided design in 2003. The research group also implemented the world's first-ever proof-of-concept MRF adder using the 0.13-m CMOS process technology for validation. The results show that the circuit can reliably operate at ultra-low supply voltage and achieve significant power saving. They received the Best Innovation Prize at the 7th MXIC IC Design Contest (the largest and the most influential annual IC design contest in Taiwan). Many research groups worldwide have followed and improved MRF design methodology since 2003. This Discovery Grant will provide operating funds over the next 5 years to support the applicant to continuously explore the potential of MRF design: especially optimizing the probabilistic design methodology, and applying the MRF design methodology to implement large-scale signal processing and communication systems. Two-thirds of the Discovery Grant will be used to train students. The applicant will use the research discoveries from this grant to facilitate access to other funding from collaborative industry and government programs. The applicant expects this grant can yield a meaningful impact on Canadian low-power electronics industry with wide ranging applications in the fields of information and communications technology and portable battery-powered healthcare devices.