CAREER: Explicit Loop Architectures for Efficiently Exploiting Instruction- and Data-Level Parallelism

职业：用于有效利用指令和数据级并行性的显式循环架构

• 批准号: 1149464
• 负责人: Christopher Batten
• 金额: $ 49.97万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-02-01 至 2017-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1149464&HistoricalAwards=false
• 关键词: CAREER; Explicit; Loop; Architectures; Efficiently

Systems across the computing spectrum, from cellphones to supercomputers, are increasingly using a heterogeneous mix of general-purpose multicores augmented with programmable graphics processing units (GPUs). General-purpose multicores are easier to program but often less energy and area efficient, while GPUs are harder to program but more efficient on specific applications. Unfortunately, the two kinds of processors have radically different programming methodologies, instruction sets, microarchitectures, and VLSI implementations, and this heterogeneity significantly increases complexity at all levels of the computing stack. The tension between programmability, efficiency, and complexity is one of the key research challenges in computer engineering today. Overcoming this challenge will help ensure the continued increase in computational capability which has enabled tremendous advances in all corners of society.While there have been some modest steps towards tighter integration between general-purpose multicores and GPUs, this project is developing a truly convergent architecture that elegantly unifies these two types of processors. At the heart of the project is a new explicit loop (XL) architectural design pattern that is based on the concept of explicitly encoding and executing a loop iteration space. The project is using a vertically integrated approach to investigate: (1) XL programming frameworks, compilers, and runtimes; (2) XL instruction sets that provide an effective software/hardware interface for expressing explicit loops; (3) XL microarchitectures that are either optimized for instruction-level parallelism (ILP) or for data-level parallelism (DLP), as well as hybrid microarchitectures that can dynamically reconfigure the same underlying hardware resources to be either ILP or DLP focused; and (4) XL VLSI implementations that will enable accurate design-space exploration of performance, area, and energy implications.This project can broadly impact the field of computer architecture by offering a novel approach for designing future computer systems that is able to improve programmability and efficiency while reducing both software and hardware complexity. The project also includes an ambitious educational outreach plan to increase high-school-student participation and undergraduate-student retention in computer engineering.

从手机到超级计算机，整个计算领域的系统越来越多地使用通用多核和可编程图形处理单元(GPU)的异类混合。通用多核更容易编程，但通常能耗和面积效率较低，而GPU更难编程，但在特定应用程序上更高效。不幸的是，这两种处理器具有完全不同的编程方法、指令集、微体系结构和VLSI实现，这种异构性显著增加了计算堆栈的所有级别的复杂性。可编程性、效率和复杂性之间的矛盾是当今计算机工程中的关键研究挑战之一。克服这一挑战将有助于确保计算能力的持续增长，这使得社会各个角落都取得了巨大的进步。虽然在通用多核和GPU之间的更紧密集成方面已经迈出了一些温和的步骤，但该项目正在开发一种真正的聚合体系结构，将这两种类型的处理器完美地统一起来。该项目的核心是一种新的显式循环(XL)架构设计模式，它基于显式编码和执行循环迭代空间的概念。该项目使用垂直集成的方法来研究：(1)XL编程框架、编译器和运行时；(2)为表示显式循环提供有效软件/硬件接口的XL指令集；(3)针对指令级并行(ILP)或数据级并行(DLP)进行优化的XL微体系结构，以及能够动态地重新配置相同的底层硬件资源以专注于ILP或DLP的混合微体系结构；和(4)XL VLSI实现，它将使性能、面积和能量的精确设计空间探索成为可能。该项目通过为设计未来的计算机系统提供一种新的方法，能够在降低软件和硬件复杂性的同时提高可编程性和效率，从而广泛地影响计算机体系结构领域。该项目还包括一项雄心勃勃的教育推广计划，以增加高中生的参与率和本科生在计算机工程方面的留存率。