CAREER: Explicit Loop Architectures for Efficiently Exploiting Instruction- and Data-Level Parallelism

从手机到超级计算机，整个计算领域的系统越来越多地使用通用多核的异构组合，并增强了可编程图形处理单元 (GPU)。通用多核更容易编程，但通常能源效率和面积效率较低，而 GPU 更难编程，但在特定应用程序上效率更高。不幸的是，这两种处理器具有截然不同的编程方法、指令集、微体系结构和 VLSI 实现，并且这种异构性显着增加了计算堆栈各个级别的复杂性。可编程性、效率和复杂性之间的紧张关系是当今计算机工程的关键研究挑战之一。克服这一挑战将有助于确保计算能力的持续增长，从而为社会各个角落带来巨大进步。虽然在通用多核和 GPU 之间更紧密的集成方面已经采取了一些适度的措施，但该项目正在开发一种真正的融合架构，可以优雅地统一这两种类型的处理器。该项目的核心是一种新的显式循环 (XL) 架构设计模式，该模式基于显式编码和执行循环迭代空间的概念。该项目正在使用垂直集成的方法来研究：（1）XL 编程框架、编译器和运行时； (2) XL指令集，为表达显式循环提供有效的软件/硬件接口； (3) 针对指令级并行性 (ILP) 或数据级并行性 (DLP) 进行优化的 XL 微架构，以及可动态重新配置相同底层硬件资源以专注于 ILP 或 DLP 的混合微架构； (4) XL VLSI 实现，将实现性能、面积和能源影响的精确设计空间探索。该项目可以通过提供一种设计未来计算机系统的新颖方法来广泛影响计算机体系结构领域，该方法能够提高可编程性和效率，同时降低软件和硬件复杂性。该项目还包括一项雄心勃勃的教育推广计划，以提高高中生对计算机工程的参与度和本科生的保留率。

Systems across the computing spectrum, from cellphones to supercomputers, are increasingly using a heterogeneous mix of general-purpose multicores augmented with programmable graphics processing units (GPUs). General-purpose multicores are easier to program but often less energy and area efficient, while GPUs are harder to program but more efficient on specific applications. Unfortunately, the two kinds of processors have radically different programming methodologies, instruction sets, microarchitectures, and VLSI implementations, and this heterogeneity significantly increases complexity at all levels of the computing stack. The tension between programmability, efficiency, and complexity is one of the key research challenges in computer engineering today. Overcoming this challenge will help ensure the continued increase in computational capability which has enabled tremendous advances in all corners of society.While there have been some modest steps towards tighter integration between general-purpose multicores and GPUs, this project is developing a truly convergent architecture that elegantly unifies these two types of processors. At the heart of the project is a new explicit loop (XL) architectural design pattern that is based on the concept of explicitly encoding and executing a loop iteration space. The project is using a vertically integrated approach to investigate: (1) XL programming frameworks, compilers, and runtimes; (2) XL instruction sets that provide an effective software/hardware interface for expressing explicit loops; (3) XL microarchitectures that are either optimized for instruction-level parallelism (ILP) or for data-level parallelism (DLP), as well as hybrid microarchitectures that can dynamically reconfigure the same underlying hardware resources to be either ILP or DLP focused; and (4) XL VLSI implementations that will enable accurate design-space exploration of performance, area, and energy implications.This project can broadly impact the field of computer architecture by offering a novel approach for designing future computer systems that is able to improve programmability and efficiency while reducing both software and hardware complexity. The project also includes an ambitious educational outreach plan to increase high-school-student participation and undergraduate-student retention in computer engineering.