SHF: Small: EVE: Ephemeral Vector Engines

SHF：小型：EVE：短暂矢量引擎

• 批准号: 2008471
• 负责人: Christopher Batten
• 金额: $ 40万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-07-01 至 2024-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008471&HistoricalAwards=false
• 关键词: SHF; Small; EVE; Ephemeral; Vector

Data-parallel kernels dominate the computational workload in a wide variety of demanding application domains, including graphics rendering, computer vision, audio processing, physical simulation, machine learning, and graph processing. Since it is no longer possible to rely on technology scaling for inevitable improvements in transistor performance and energy efficiency, there is renewed interest in specialized hardware to improve performance and efficiency compared to general-purpose processors for codes with significant amounts of data-level parallelism (DLP). Unfortunately, this specialized hardware lies idle when these computing systems are executing the many other interesting workloads that lack DLP. This project is exploring a new approach that is able to create specialized hardware "on-demand" by reconfiguring the memory already contained within modern computer systems to handle both storage and computation. The project's broader significance and importance are rooted in the need for computer architects to creatively mitigate the challenges imposed by the looming end of Moore's law, and the potential transformative impact of a software/hardware co-design approach.Two popular styles of hardware accelerators for exploiting DLP include data-parallel acceleration (DPA), which focuses on moving data in main memory to the compute hardware, and processing-in-memory (PIM), which focuses on moving compute hardware to the data in memory. In-situ processing-in-memory (PIM) is a recently proposed approach that attempts to significantly reduce the area overhead associated with exploiting data-level parallelism while at the same time reaping most of the benefit. In-situ PIM uses bit-line computation to perform basic bit-wise logical operations in a single read of a traditional memory array. Each memory column can be further transformed into a bit-serial ALU by adding extra logic, multiplexing, and state elements in the peripheral circuitry. This project makes two key observations about prior work on in-situ PIM: (1) in-situ PIM lacks compelling programming models; and (2) in-situ PIM requires massive parallelism to outweigh bit-serial execution overheads.This project is exploring ephemeral vector engines (EVE) as a new approach to address these challenges. EVE enables dynamically repurposing one or more private L2 cache ways to serve as on-demand (i.e., ephemeral) vector engines implemented using a novel reconfigurable bit-serial/bit-parallel in-situ processing-in-SRAM. EVE supports the unmodified RISC-V vector instruction set and can be rapidly reconfigured to use either bit-serial or bit-parallel execution. Bit-serial execution provides higher throughput but longer latencies, while bit-parallel execution provides lower throughput but shorter latencies. This project is using a vertically integrated research methodology spanning circuits, microarchitecture, architecture, and applications to explore three research thrusts. Thrust 1: EVE Circuits is exploring how to implement reconfigurable bit-serial/bit-parallel compute logic in the periphery of the SRAM array so as to minimize area, energy, and timing overhead. Thrust 2: EVE Microarchitecture is exploring how to efficiently map higher-level vector instructions into lower-level micro-operations. Thrust 3: EVE Architecture is exploring how to integrate the EVE microarchitecture into a complete system accelerating applications with regular DLP, while adding little to no area, energy, performance overhead for applications without regular DLP.This project is also pursuing two broader impact initiatives. The first is an ambitious yet concrete effort to increase participation of women in computer engineering by organizing a week-long computer engineering design experience for high-school girls. The second is an initiative to better preparing Cornell graduates for the post-Moore's law era, by integrating open-source CAD tools and the emerging PIM architectural approach into the undergraduate and graduate curriculum.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

数据并行核在各种要求苛刻的应用领域中主导着计算工作负载，包括图形渲染、计算机视觉、音频处理、物理模拟、机器学习和图形处理。由于不再可能依靠技术扩展来实现晶体管性能和能效的不可避免的改进，因此与具有大量数据级并行性（DLP）的代码的通用处理器相比，专门的硬件重新引起了人们的兴趣，以提高性能和效率。不幸的是，当这些计算系统执行缺乏DLP的许多其他有趣的工作负载时，这种专用硬件处于空闲状态。这个项目正在探索一种新的方法，通过重新配置现代计算机系统中已经包含的内存来处理存储和计算，从而能够“按需”创建专门的硬件。该项目的广泛意义和重要性源于计算机架构师需要创造性地减轻摩尔定律即将结束所带来的挑战，以及软件/硬件协同设计方法的潜在变革影响。用于利用DLP的两种流行的硬件加速器包括数据并行加速（DPA）和内存处理（PIM），前者侧重于将主内存中的数据移动到计算硬件，后者侧重于将计算硬件移动到内存中的数据。内存中的原位处理（PIM）是最近提出的一种方法，它试图显著减少与利用数据级并行性相关的区域开销，同时获得大部分好处。原位PIM使用位线计算在传统存储器阵列的单次读取中执行基本的逐位逻辑操作。通过在外围电路中添加额外的逻辑、多路复用和状态元素，每个存储列可以进一步转换为位串行ALU。本项目对先前的原位PIM工作进行了两个关键观察：(1)原位PIM缺乏令人信服的规划模型；(2)原位PIM需要大量并行性来抵消位串行执行开销。该项目正在探索短暂矢量引擎（EVE）作为解决这些挑战的新方法。EVE可以动态地重新利用一个或多个私有L2缓存方式作为按需（即短暂的）矢量引擎，使用一种新颖的可重构sram中的位串行/位并行原位处理来实现。EVE支持未经修改的RISC-V矢量指令集，可以快速重新配置为使用位串行或位并行执行。位串行执行提供更高的吞吐量但更长的延迟，而位并行执行提供更低的吞吐量但更短的延迟。该项目采用垂直集成的研究方法，涵盖电路、微架构、架构和应用，探索三个研究重点。重点1:EVE电路正在探索如何在SRAM阵列的外围实现可重构的位-串行/位-并行计算逻辑，以最大限度地减少面积、能量和时序开销。重点2:EVE微架构正在探索如何有效地将高级向量指令映射到低级微操作中。推进3:EVE架构正在探索如何将EVE微架构集成到一个完整的系统中，加速具有常规DLP的应用程序，同时为没有常规DLP的应用程序增加很少甚至没有面积，能量和性能开销。该项目还在推行两项影响范围更广的倡议。第一个目标是通过为高中女生组织为期一周的计算机工程设计体验活动，提高女性在计算机工程领域的参与度。第二个是通过将开源CAD工具和新兴的PIM架构方法整合到本科和研究生课程中，为康奈尔大学的毕业生更好地为后摩尔定律时代做好准备。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

使用 SRAM 中的原位处理实现可重新配置的位串行/位并行矢量加速器

• DOI: 10.1109/iscas45731.2020.9181068
• 发表时间: 2020
• 期刊: 2020 IEEE International Symposium on Circuits and Systems (ISCAS
• 作者: Al-Hawaj, Khalid;Afuye, Olalekan;Agwa, Shady;Apsel, Alyssa;Batten, Christopher
• 通讯作者: Batten, Christopher

EVE: Ephemeral Vector Engines

• DOI: 10.1109/hpca56546.2023.10071074
• 发表时间: 2023-02
• 期刊: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
• 作者: Khalid Al-Hawaj;T. Ta;Nick Cebry;Shady O. Agwa;O. Afuye;Eric Hall;Courtney Golden;A. Apsel;C. Batten

big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip

• DOI: 10.1109/micro56248.2022.00025
• 发表时间: 2022-10
• 期刊: 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: T. Ta;Khalid Al-Hawaj;Nick Cebry;Yanghui Ou;Eric Hall;Courtney Golden;C. Batten

CAPE: A Content-Addressable Processing Engine

CAPE：内容可寻址处理引擎

• DOI: 10.1109/hpca51647.2021.00054
• 发表时间: 2021
• 期刊: IEEE Int'l Symp. on High-Performance Computer Architecture (HPCA
• 作者: Caminal, Helena;Yang, Kailin;Srinivasa, Srivatsa;Ramanathan, Akshay Krishna;Al-Hawaj, Khalid;Wu, Tianshu;Narayanan, Vijaykrishnan;Batten, Christopher;Martinez, Jose F.
• 通讯作者: Martinez, Jose F.