SHF: Small: Programming with Non-Coherent Memory

SHF：小型：使用非相干内存编程

• 批准号: 1216613
• 负责人: Suresh Jagannathan
• 金额: $ 45万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1216613&HistoricalAwards=false
• 关键词: SHF; Small; Programming; Non; Coherent

The preponderance of language design and program analysis efforts in the study of multicore systems has implicitly assumed the presence of an underlying coherent memory that ensures global visibility of updates performed on processor-local caches. Because all threads witness a consistent view of data, concurrency bugs manifest purely as a consequence of unintended non-determinism introduced by scheduler-driven thread interleavings and inadequate synchronization. As new architectural advances lead to multicore or manycore platforms supporting hundreds of (potentially heterogenous) cores, automatically enforcing memory coherence becomes an increasingly complex and expensive proposition. Indeed, new architectural designs are likely to sacrifice local coherence guarantees in exchange for a simple commodity-based scalable design, equipped with a limited degree of global shared memory. Applications that target such platforms must be carefully written not to make assumptions about the consistency of the contents of memory locations accessed and modified locally. In the absence of coherence, new techniques are needed to recover the abstraction benefits that are now lost; these issues become exacerbated at scale. The broader impacts of the proposal have obvious positive interaction with industry efforts to promote multicore and manycore processor platforms.This project will consider novel ways to map consistency models expressed in the context of high-level managed languages onto non-coherent architectural platforms. In doing so, it will consider new programming models, abstractions, analyses, and implementations to enable (a) avoidance of coherency enforcement whenever possible, (b) reduction of coherency demands based on application logic, (c) specification of complex consistency requirements that can be used to inform the implementation of specialized software-based coherence protocols, and (d) integration of language-level memory models with weakly-coherent architectures. The project will subsume formal, rigorous development of different abstractions, analyses, and implementations that enable the automatic construction of new protocol families that express complex aggregates of communication and computation actions with sensible consistency semantics even when executed on non-coherent platforms.

在多核系统的研究中，语言设计和程序分析工作的优势已经隐含地假设了一个底层的一致性内存的存在，该内存确保了在处理器本地缓存上执行的更新的全局可见性。 因为所有线程都见证了一致的数据视图，并发错误纯粹是由于由线程驱动的线程交织和不充分的同步引入的意外的非确定性造成的。 随着新架构的进步导致多核或众核平台支持数百个（可能是异构的）内核，自动执行内存一致性变得越来越复杂和昂贵。 事实上，新的架构设计很可能牺牲本地一致性保证，以换取一个简单的基于商品的可扩展设计，配备了有限程度的全局共享内存。 针对这些平台的应用程序必须小心编写，不要对本地访问和修改的内存位置的内容的一致性做出假设。 在缺乏一致性的情况下，需要新的技术来恢复现在失去的抽象好处;这些问题在规模上变得更加严重。 该提案的更广泛影响与业界推广多核和众核处理器平台的努力有着明显的积极互动。该项目将考虑将高级托管语言上下文中表达的一致性模型映射到非一致性架构平台的新方法。 在这样做时，它将考虑新的编程模型、抽象、分析和实现，以实现（a）尽可能避免一致性实施，（B）减少基于应用逻辑的一致性需求，（c）复杂一致性要求的规范，其可用于通知基于专门软件的一致性协议的实现，以及（d）语言级存储器模型与弱一致架构的集成。 该项目将对不同的抽象、分析和实现进行严格的形式化、严格的开发，这些抽象、分析和实现能够自动构建新的协议族，这些协议族即使在不一致的平台上执行时，也能表达具有合理一致性语义的通信和计算操作的复杂集合。