EAGER: Towards Low-Latency Low-Power Heterogeneous Memory Access

EAGER：迈向低延迟低功耗异构内存访问

• 批准号: 1249223
• 负责人: Meikang Qiu
• 金额: $ 10万
• 依托单位: University of Kentucky Research Foundation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-08-15 至 2013-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1249223&HistoricalAwards=false
• 关键词: EAGER; Towards; Low; Latency; Power

This project will explore the application of heterogeneous memory architectures to reduce power consumption while maintaining adequate response times in embedded computer systems. The slower response times of memory devices as compared to the speeds of processing elements is recognized as a major performance bottleneck. Power used by memory devices, especially static power, is recognized as a major source of energy consumption in computers. There are a variety of different types of memory technologies, each occupying a discrete point in a multidimensional trade-off space represented by parameters such as memory access latency, memory bandwidth, power consumption, memory lifetime, and cost of memory devices. Heterogeneous memory systems represent a potentially transformative development because combining several different types of memory opens up a much broader range of this trade-off space. The focus of this preliminary study is on efficient use of heterogeneous memory types in a scratch-pad memory. Expected outcomes include: 1) A new heterogeneous memory hierarchy that integrates on-chip Static Random Access Memory (SRAM), Magnetic Random Access Memory (MRAM), Zero-capacitor RAM (Z-RAM) technologies, as well as off-chip DRAM. 2) a set of algorithms that achieve allocation for optimal memory access speed or efficient space utilization. 3) a simulation toolkit that integrates commonly used simulation benchmarks, such as MiBench, PARSEC, and MediaBench.The broader impacts of this research include potential for contributing technology that reduces energy consumption for current embedded computing applications, and may enable more advanced future embedded computing systems within energy, power, and thermal dissipation constraints. The project will integrate research with graduate education, both in the classroom and through direct participation of students in the research. It will include collaborations with researchers at IBM, Pacific Northwest Laboratories, and Intel.

该项目将探索在嵌入式计算机系统中应用异种存储体系结构来降低功耗，同时保持足够的响应时间。与处理元件的速度相比，存储设备的响应时间较慢被认为是主要的性能瓶颈。存储设备使用的功率，特别是静态功率，被认为是计算机能量消耗的主要来源。存在各种不同类型的存储器技术，每一种都占据由诸如存储器访问延迟、存储器带宽、功率消耗、存储器寿命和存储器设备成本等参数表示的多维权衡空间中的离散点。异类存储系统代表着一种潜在的变革性发展，因为将几种不同类型的存储结合在一起，可以打开更广泛的这种权衡空间。这项初步研究的重点是在高速暂存存储器中有效使用不同类型的存储器。预期结果包括：1)集成了片上静态随机存取存储器(SRAM)、磁随机存取存储器(MRAM)、零电容RAM(Z-RAM)技术以及片外DRAM的新的异质存储器层次结构。2)实现最优内存访问速度或高效空间利用的分配的一组算法。3)集成了常用仿真基准的仿真工具包，如MiBtch、PARSEC和MediaBench。本研究的更广泛影响包括为当前的嵌入式计算应用提供降低能耗的技术的潜力，并可能在能量、功率和散热的约束下实现更先进的未来嵌入式计算系统。该项目将把研究与研究生教育结合起来，既包括在课堂上，也包括通过学生直接参与研究。它将包括与IBM、太平洋西北实验室和英特尔的研究人员的合作。