Cross-Layer Fault Resilience for Interconnection Networks in Multi-core SoCs

多核 SoC 中互连网络的跨层故障恢复

• 批准号: 1252500
• 负责人: Sudeep Pasricha
• 金额: $ 18万
• 依托单位: Colorado State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-04-01 至 2017-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1252500&HistoricalAwards=false
• 关键词: Cross; Layer; Fault; Resilience; Interconnection

Shrinking fabrication feature sizes and the increasing proliferation of mixed-signal and 3D integration are elevating rates of faults, variation, and aging related degradation in electronic integrated circuits, threatening the reliability of communication between processing cores in system-on-chip (SoC) architectures. The goal of this project is to realize system-level computer-aided design (CAD) automation techniques and tools to assist chip designers to trade off reliability with competing design constraints for on-chip interconnection networks within tight time-to-market constraints. This novel framework will exploit cross-layer insights about the software application, hardware intellectual property blocks, and circuits, as well as knowledge of key factors impacting susceptibility to runtime faults for network routers and interfaces. By achieving reliability goals and multi-objective design trade-offs for on-chip interconnection network fabrics with orders of magnitude lower time complexity and overhead than is possible today, this project will transform the design of multi-core SoCs that already permeate most facets of our daily lives. The research will drive a tightly integrated education plan to inspire K-12 students toward STEM careers, ensure workforce continuity, and increase participation of veterans, undergraduates, and women via capstone projects and distance education initiatives. A new course on fault tolerant chip design will be created and existing courses on computer architecture and embedded systems will be enhanced with reliability-centric components. By exposing graduate students to diverse aspects of CAD algorithms, SoC architectures, and parallel applications, the educational component of this project will contribute to an agile high-tech workforce that will maintain continued US leadership in technological innovation.

制造特征尺寸的缩小以及混合信号和3D集成的日益普及，提高了电子集成电路中故障、变异和老化相关退化的发生率，威胁到片上系统（SoC）架构中处理核心之间通信的可靠性。该项目的目标是实现系统级计算机辅助设计（CAD）自动化技术和工具，以帮助芯片设计人员在严格的上市时间限制内权衡芯片上互连网络的可靠性和竞争设计约束。这个新颖的框架将利用软件应用程序、硬件知识产权块和电路的跨层洞察力，以及影响网络路由器和接口对运行时故障敏感性的关键因素的知识。通过实现片上互连网络结构的可靠性目标和多目标设计权衡，同时降低时间复杂性和开销，该项目将改变已经渗透到我们日常生活的大多数方面的多核soc的设计。这项研究将推动一项紧密整合的教育计划，以激励K-12学生走向STEM职业，确保劳动力的连续性，并通过顶点项目和远程教育计划提高退伍军人、本科生和女性的参与度。将开设一门新的容错芯片设计课程，现有的计算机体系结构和嵌入式系统课程将以可靠性为中心的组件来加强。通过让研究生接触到CAD算法、SoC架构和并行应用的各个方面，这个项目的教育部分将有助于培养一支敏捷的高科技劳动力，这将保持美国在技术创新方面的领导地位。