Cross-Layer Fault Resilience for Interconnection Networks in Multi-core SoCs

制造特征尺寸的缩小以及混合信号和3D集成的日益普及正在提高电子集成电路中与故障、变化和老化相关的退化的比率，威胁到片上系统(SoC)体系结构中处理核之间通信的可靠性。该项目的目标是实现系统级计算机辅助设计(CAD)自动化技术和工具，以帮助芯片设计者在严格的上市时间限制内权衡芯片内互连网络的可靠性和竞争设计约束。这一新颖的框架将利用对软件应用程序、硬件知识产权块和电路的跨层洞察，以及影响网络路由器和接口的运行时故障敏感性的关键因素的知识。通过实现芯片互连网络交换矩阵的可靠性目标和多目标设计折衷，该项目将改变已经渗透到我们日常生活的大多数方面的多核SoC的设计，其时间复杂性和开销比目前可能低一个数量级。这项研究将推动一个紧密结合的教育计划，以激励K-12学生走向STEM职业生涯，确保劳动力连续性，并通过顶峰项目和远程教育倡议增加退伍军人、本科生和女性的参与。将开设一门关于容错芯片设计的新课程，并将用以可靠性为中心的组件来加强现有的计算机体系结构和嵌入式系统课程。通过让研究生接触CAD算法、SoC架构和并行应用的不同方面，该项目的教育部分将有助于培养一支灵活的高科技劳动力队伍，保持美国在技术创新方面的持续领导地位。

Shrinking fabrication feature sizes and the increasing proliferation of mixed-signal and 3D integration are elevating rates of faults, variation, and aging related degradation in electronic integrated circuits, threatening the reliability of communication between processing cores in system-on-chip (SoC) architectures. The goal of this project is to realize system-level computer-aided design (CAD) automation techniques and tools to assist chip designers to trade off reliability with competing design constraints for on-chip interconnection networks within tight time-to-market constraints. This novel framework will exploit cross-layer insights about the software application, hardware intellectual property blocks, and circuits, as well as knowledge of key factors impacting susceptibility to runtime faults for network routers and interfaces. By achieving reliability goals and multi-objective design trade-offs for on-chip interconnection network fabrics with orders of magnitude lower time complexity and overhead than is possible today, this project will transform the design of multi-core SoCs that already permeate most facets of our daily lives. The research will drive a tightly integrated education plan to inspire K-12 students toward STEM careers, ensure workforce continuity, and increase participation of veterans, undergraduates, and women via capstone projects and distance education initiatives. A new course on fault tolerant chip design will be created and existing courses on computer architecture and embedded systems will be enhanced with reliability-centric components. By exposing graduate students to diverse aspects of CAD algorithms, SoC architectures, and parallel applications, the educational component of this project will contribute to an agile high-tech workforce that will maintain continued US leadership in technological innovation.