SHF: Small: Energy-Efficient and Reliable Communication with Silicon Photonics for Terascale Datacenters-on-Chip

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Electronic processing chips are at the heart of the digital intelligence that has been the driving force for groundbreaking technological advances across the medical, consumer, industrial, networking, aerospace, automotive, and defense application domains. In recent years, there has been a growing trend in these application domains of massive data generation and consumption, which puts immense pressure on the networks at the chip-scale that must now transfer very high volumes of data in much shorter durations of time than ever before. Traditional electrical networks at the chip-scale are breaking down under this pressure, which is catastrophic as it prevents the development of the next generation of high-performance digital intelligence that can transform society and improve lives. Fortunately, silicon photonics has emerged as an exciting technological panacea that can replace slow electrical links with much faster light-speed transfers. While communication over long optical fibers (e.g., several miles) is quite common today, the nano-integration of silicon photonics technology with electronic chips is a new paradigm and presents enormous challenges that have yet to be addressed. This project will involve transformative research to overcome these fundamental challenges, and pave the way for realizing future photonics-based electronic chips that are miniature in size, but with the same computing power as a large datacenter computing facility today. Close collaborations with industrial partners at HP Enterprise and Lumerical will aid in the rapid adoption of the outcomes. Moreover, by exposing K-12, undergraduate, and graduate students to the diverse aspects of emerging technologies, devices, circuits, architectures, and algorithms, the project will contribute to an agile high-tech workforce that will maintain continued US leadership in technological innovation.The principal contribution of this project will be a new framework that will push the boundaries of achieving ultra-low energy and high reliability data transfers with silicon photonics at the chip-scale. This framework consists of three major thrusts that are closely related and will be addressed in a highly integrated manner: (1) Characterize behavior of silicon photonics devices and explore new device configurations based on device fabrication at Applied NanoTools Inc., to enable the selection of energy-efficient and low-cost devices; (2) Design new circuits with silicon photonics devices to overcome noise, increase bandwidth, and reduce power dissipation during communication; and (3) Create new silicon photonics-based network architectures and tools for their optimization, to realize ultra-low energy and fault-resilience solutions for transferring data between processing cores at the chip-scale. Beyond these three thrusts, the framework will exploit cross-layer insights across the device, circuit, and architecture layers, and devise optimizations that span across two or more of these layers. The innovations at the individual layers together with optimizations across layers will achieve more aggressive energy savings and higher reliability chip-scale communication than what is possible today. This outcome will usher in a new era of ultra-high performance computing where light speed data transfers within electronic chips can work together with optics-based data transfers external to the chip, to overcome communication energy and performance bottlenecks at all levels. Such a development will enable lower-cost supercomputing and cloud datacenters, making computing more affordable for scientists and more ubiquitous in everyday life, to transform our lives in innumerable ways.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.