Design Automation for Cost-Effective Implementation of Adaptive Integrated Circuits

用于经济高效地实现自适应集成电路的设计自动化

• 批准号: 1255193
• 负责人: Jiang Hu
• 金额: $ 18万
• 依托单位: Texas A&M University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-04-01 至 2017-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1255193&HistoricalAwards=false
• 关键词: Design; Automation; Cost; Effective; Implementation

Variability is a grand challenge that hinders the progress of semiconductor technology. Adaptive design is considered a promising approach for addressing this challenge, especially under increasingly tight chip power constraints. However, its application in practice is limited, largely due to the lack of systematic techniques for managing its overhead, complexity, and integration with existing design flows. This research will develop a design automation framework that optimizes the use of adaptivity resources, maximizes their efficiency, and balances the tradeoff with conventional design objectives. The key of this research is capturing the uncertainty and dynamics of adaptive designs in a lightweight manner, yet with high fidelity. New variability and adaptivity models will be investigated in conjunction with robust optimization methods. In addition, a formal technique will be studied to handle the tradeoffs among competing design objectives. Parallel computing techniques will also be explored to cope with the enormous problem sizes of current and emerging applications. This research will strengthen some weak links in adaptive circuit technology and help pave a path toward its wide applications. It will simultaneously address variability and power challenges faced by nanometer semiconductor technologies. The potential improvement of chip power-efficiency will facilitate green computing technology. Furthermore, the proposed techniques will be applicable to next-generation device technologies and will therefore benefit the future of the semiconductor industry. This research will also serve as a test-bed for training students to understand synergies among various aspects of modern chip design processes.

可变性是阻碍半导体技术进步的巨大挑战。自适应设计被认为是解决这一挑战的一种有前途的方法，特别是在越来越严格的芯片功率限制下。然而，它在实践中的应用是有限的，主要是由于缺乏管理其开销、复杂性和与现有设计流集成的系统技术。本研究将开发一个设计自动化框架，优化自适应资源的使用，最大化其效率，并平衡与传统设计目标的权衡。这项研究的关键在于以一种轻量级的方式捕捉自适应设计的不确定性和动态，同时又具有高保真度。新的变异性和自适应模型将与鲁棒优化方法一起研究。此外，将研究一种正式的技术来处理竞争设计目标之间的权衡。并行计算技术也将探讨，以应付巨大的问题规模的当前和新兴的应用程序。本研究将加强自适应电路技术的薄弱环节，为其广泛应用铺平道路。它将同时解决纳米半导体技术所面临的可变性和功率挑战。芯片功率效率的潜在提高将促进绿色计算技术的发展。此外，所提出的技术将适用于下一代器件技术，因此将有利于半导体行业的未来。这项研究也将作为一个试验台，训练学生了解现代芯片设计过程的各个方面之间的协同作用。