CSR: Medium: Multicore Real Time Virtual Partitions

CSR：中：多核实时虚拟分区

• 批准号: 1302563
• 负责人: Lui Sha
• 金额: $ 104.95万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-09-01 至 2017-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1302563&HistoricalAwards=false
• 关键词: CSR; Medium; Multicore; Real; Time

Multicore computer chips pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory driver bandwidth, and shared I/O bandwidth. The project addresses this challenge by 1) integrating resource partition mechanisms and their implementation, 2) optimizing resource allocation algorithms, and 3) developing schedulability analysis technology to create real time virtual partitions (RTVPs) on each core. The goal is for each RTVP to be able to be analyzed as if it were a standalone single core chip, independent of the workloads in other cores and partitions. In a multicore chip, a task's worst case execution time (WCET) depends on the partition's allocated memory driver bandwidth, the last level cache size, and I/O bandwidth. To optimize the resources allocated to a RTVP, one needs to know if the tasks in the RTVP are schedulable with a given resource allocation. To perform schedulability analysis, one needs to know tasks' WCETs. To determine tasks' WCETs, one needs to know the resources allocated to the RTVP. The approach taken by this project to break such circular dependency is to first find an initial pessimistic but feasible solution, then apply an interactive optimization method to find a near optimal solution. Our nation has a large body of certified real time safety and mission critical software developed for single core chips, using certification procedures developed for single core chips. Now those chips are becoming obsolete, and newer chips are being designed with slower clock rates but multiple cores. Without a technology like RTVP, the change of workload in one core could adversely impact the schedulability of tasks in other cores, triggering the recertification of applications in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the aircraft industry. To help ensure the usability of this project's research outcomes, the project team has collaborative contacts with Freescale Semiconductor whose multicore chips are widely used in avionics, Lockheed Martin who develops multicore chip based avionics for the US Department of Defense, and with Rockwell Collins who cooperates with Boeing and the FAA on the development and certification of multicore chip based civilian avionics, as well as the FAA. Key elements of the research are to be incorporated into the educational program of the host institution.

多核计算机芯片对硬实时系统提出了新的挑战，因为处理核心的共享末级高速缓存、共享存储器驱动器带宽和共享I/O带宽之间存在复杂的时间耦合。 该项目通过1）集成资源分区机制及其实现，2）优化资源分配算法，以及3）开发可扩展性分析技术以在每个核心上创建真实的时间虚拟分区（RTVP）来解决这一挑战。我们的目标是让每个RTVP都能够像独立的单核芯片一样进行分析，独立于其他内核和分区中的工作负载。在多核芯片中，任务的最坏情况执行时间（WCET）取决于分区分配的内存驱动器带宽、最后一级缓存大小和I/O带宽。为了优化分配给RTVP的资源，需要知道RTVP中的任务是否可与给定的资源分配并行。为了执行可并行性分析，需要知道任务的WCET。为了确定任务的WCET，需要知道分配给RTVP的资源。本项目打破这种循环依赖的方法是首先找到一个初始的悲观但可行的解决方案，然后应用交互式优化方法找到一个接近最优的解决方案。 我们国家有大量的认证真实的时间安全和使命关键软件开发的单核芯片，使用认证程序开发的单核芯片。现在这些芯片已经过时了，新的芯片正在设计更慢的时钟速率，但多个核心。如果没有像RTVP这样的技术，一个核心中的工作负载变化可能会对其他核心中的任务的可扩展性产生不利影响，从而触发其他核心中的应用程序的重新认证。这种重新认证的时间和费用在经济上是不可持续的。 这个问题对航空工业来说尤其重要。 为了确保本项目研究成果的可用性，项目团队与飞思卡尔半导体公司（其多核芯片广泛应用于航空电子设备）、洛克希德马丁公司（其为美国国防部开发基于多核芯片的航空电子设备）以及罗克韦尔柯林斯公司（其与波音公司和FAA以及FAA合作开发和认证基于多核芯片的民用航空电子设备）进行了合作联系。研究的关键要素将纳入东道机构的教育方案。