CSR: Medium: Multicore Real Time Virtual Partitions

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Multicore computer chips pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory driver bandwidth, and shared I/O bandwidth. The project addresses this challenge by 1) integrating resource partition mechanisms and their implementation, 2) optimizing resource allocation algorithms, and 3) developing schedulability analysis technology to create real time virtual partitions (RTVPs) on each core. The goal is for each RTVP to be able to be analyzed as if it were a standalone single core chip, independent of the workloads in other cores and partitions. In a multicore chip, a task's worst case execution time (WCET) depends on the partition's allocated memory driver bandwidth, the last level cache size, and I/O bandwidth. To optimize the resources allocated to a RTVP, one needs to know if the tasks in the RTVP are schedulable with a given resource allocation. To perform schedulability analysis, one needs to know tasks' WCETs. To determine tasks' WCETs, one needs to know the resources allocated to the RTVP. The approach taken by this project to break such circular dependency is to first find an initial pessimistic but feasible solution, then apply an interactive optimization method to find a near optimal solution. Our nation has a large body of certified real time safety and mission critical software developed for single core chips, using certification procedures developed for single core chips. Now those chips are becoming obsolete, and newer chips are being designed with slower clock rates but multiple cores. Without a technology like RTVP, the change of workload in one core could adversely impact the schedulability of tasks in other cores, triggering the recertification of applications in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the aircraft industry. To help ensure the usability of this project's research outcomes, the project team has collaborative contacts with Freescale Semiconductor whose multicore chips are widely used in avionics, Lockheed Martin who develops multicore chip based avionics for the US Department of Defense, and with Rockwell Collins who cooperates with Boeing and the FAA on the development and certification of multicore chip based civilian avionics, as well as the FAA. Key elements of the research are to be incorporated into the educational program of the host institution.