SBIR Phase I: Graphene On-Chip Interconnects

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This Small Business Innovation Research Phase I project proposes to replace Cu on-chip interconnects with a graphene technology. Nanoscale Cu interconnects that make electrical connections to active devices, mainly transistors, are an essential component of nearly all semiconductor chips. In Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs), this Cu interconnect fabric is applied as a separate component to the transistors that are embedded in the Si wafer. As the dimensions of these transistors are continually scaled down to improve performance (a trend that major chip manufacturers agree will continue for the next few decades), the Cu interconnect fabric must also be scaled in parallel. Whereas transistors improve performance with scaling, the electrical resistance of Cu interconnects rapidly increases when scaled due to intrinsic properties of the metal. This brings an abundance of interconnect pain points to chip manufacturers, limiting their competitive edge for high-performance and low-power processors. This project develops graphene on-chip interconnects that can replace Cu and facilitate future IC scaling. The broader impact/commercial potential of this project is the enabling of a tremendously diverse portfolio of technologies including, but not limited to, mobile computing / smartphones, implantable biomedical devices, and hybrid engine controllers and semiconductor chips cross-pollinate well into broad commercial applications. Scaling the dimensions of transistors and interconnects has defined the success that microelectronics (and now nanoelectronics) have enjoyed for nearly half a century. Technologies that facilitate continued scaling and keeping pace with Moore's Law are a must for chip manufacturers to maintain a competitive edge. With scaling comes faster performance, expanded capabilities, and greater reliability to all of the diverse applications that are driven by such chip technology.