SBIR Phase I: Graphene On-Chip Interconnects

SBIR 第一阶段：石墨烯片上互连

• 批准号: 1315042
• 负责人: Kevin Brenner
• 金额: $ 15万
• 依托单位: Harper Laboratories
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-07-01 至 2014-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1315042&HistoricalAwards=false
• 关键词: SBIR; Phase; Graphene; Chip; Interconnects

This Small Business Innovation Research Phase I project proposes to replace Cu on-chip interconnects with a graphene technology. Nanoscale Cu interconnects that make electrical connections to active devices, mainly transistors, are an essential component of nearly all semiconductor chips. In Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs), this Cu interconnect fabric is applied as a separate component to the transistors that are embedded in the Si wafer. As the dimensions of these transistors are continually scaled down to improve performance (a trend that major chip manufacturers agree will continue for the next few decades), the Cu interconnect fabric must also be scaled in parallel. Whereas transistors improve performance with scaling, the electrical resistance of Cu interconnects rapidly increases when scaled due to intrinsic properties of the metal. This brings an abundance of interconnect pain points to chip manufacturers, limiting their competitive edge for high-performance and low-power processors. This project develops graphene on-chip interconnects that can replace Cu and facilitate future IC scaling. The broader impact/commercial potential of this project is the enabling of a tremendously diverse portfolio of technologies including, but not limited to, mobile computing / smartphones, implantable biomedical devices, and hybrid engine controllers and semiconductor chips cross-pollinate well into broad commercial applications. Scaling the dimensions of transistors and interconnects has defined the success that microelectronics (and now nanoelectronics) have enjoyed for nearly half a century. Technologies that facilitate continued scaling and keeping pace with Moore's Law are a must for chip manufacturers to maintain a competitive edge. With scaling comes faster performance, expanded capabilities, and greater reliability to all of the diverse applications that are driven by such chip technology.

这个小企业创新研究第一阶段项目提出用石墨烯技术取代Cu片上互连。 与有源器件（主要是晶体管）进行电连接的纳米级Cu互连是几乎所有半导体芯片的重要组成部分。 在互补金属氧化物半导体（CMOS）集成电路（IC）中，这种Cu互连结构作为单独的部件应用于嵌入在Si晶片中的晶体管。 随着这些晶体管的尺寸不断缩小以提高性能（主要芯片制造商认为这一趋势将在未来几十年内持续下去），Cu互连结构也必须并行扩展。尽管晶体管通过缩放来提高性能，但是Cu互连的电阻在缩放时由于金属的固有特性而迅速增加。 这给芯片制造商带来了大量的互连痛点，限制了他们在高性能和低功耗处理器方面的竞争优势。 该项目开发了石墨烯片上互连，可以取代Cu并促进未来的IC规模化。 该项目更广泛的影响/商业潜力是实现极其多样化的技术组合，包括但不限于移动的计算/智能手机、植入式生物医学设备以及混合发动机控制器和半导体芯片，这些技术可以很好地交叉应用于广泛的商业应用。缩小晶体管和互连的尺寸定义了微电子学（现在是纳米电子学）近半个世纪以来的成功。促进持续扩展并与摩尔定律保持同步的技术是芯片制造商保持竞争优势的必要条件。 随着规模的扩大，这种芯片技术所驱动的所有不同应用程序都具有更快的性能、更大的功能和更高的可靠性。