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SHF: Small: Bio-Inspired Logic Design with Graph and Field Theory

SHF: Small: Bio-Inspired Logic Design with Graph and Field Theory
SHF:小:利用图和场论进行仿生逻辑设计
批准号:
1319884
负责人:
Mingjie Lin
金额:
$27.16万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2013
资助国家:
美国
项目状态:
已结题
起止时间:
2013-09-15 至 2018-08-31

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中文摘要
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英文摘要
As nano-scale field-effect devices quickly approach their physical limits in feature size, their stochastic device characteristics will pose severe challenges to constructing robust digital circuitry. Unlike transistor defects due to fabrication imperfection, quantum-related switching uncertainties will seriously increase their susceptibility to noise, thus rendering the traditional thinking and logic design techniques inadequate. This work aims at developing a new logic design paradigm that achieves circuit robustness for stochastically imperfect transistors and interconnects. To this end, the PI reformulates the traditional boolean-based digital design problem as a probabilistic logic-labeling problem and attempts to solve it with two approaches: a graph-theoretic approach, and a field-theoretic approach. The project also studies two unconventional logic design methodologies: a bio-inspired logic scaffolding and a self-correcting logic design. The PI will disseminate findings by developing new curricula and creating compelling interactive learning materials e.g., hardware-based emulations, software simulations, and interdisciplinary study opportunities to expose students to the new area of stochastic logic design. The PI will also create mentoring and outreach programs specifically targeted to attract underrepresented groups, thus preparing a new diverse workforce for future IC industry.
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会议论文
SHF: Small: Graph-X: Exploiting Hidden Parallelism of Irregular and Non-Stencil Computation in High-Level Synthesis
CAREER: iMPACT: Metaphysical and Probabilistic-Based Computing Transformation with Emerging Spin-Transfer Torque Device Technology
BRIGE: Minimum-Energy Bio-Inspired Analogic Computing Devices with Stochastic Switching Transistors under Ultra-Low VDD
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